Semiconductor Memory Columnar Structure Spacing Optimization
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Solution Overview
Problem
Stacked-type semiconductor memory devices face challenges in achieving high-speed operation due to the limitations in the design of conductive and insulating films, which affect the performance of memory cells and overall device efficiency.
Innovation Solution
The semiconductor memory device incorporates a stacked body with alternately layered conductive and insulating films, featuring columnar structures with a charge storage film and specific insulating film configurations that optimize the distance and positioning of electrode films to enhance memory cell performance and operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the columnar structures are arranged with uniform spacing, then the manufacturing process is simplified, but the resistance and capacitance characteristics of memory cells cannot be optimized for high-speed operation
Solution Approach 1:
The patent applies local quality by creating different spacing configurations of columnar structures in different regions. Specifically, first columnar structures have a first spacing while second columnar structures have a second spacing that is different from the first. This allows different memory cells to have optimized resistance and capacitance characteristics tailored to their specific functional requirements, thereby achieving high-speed operation while maintaining manufacturing feasibility through localized variations rather than global redesign.
2Device complexity
If the insulating film divides all electrode films uniformly, then the structure is simplified and manufacturing is easier, but the resistance and capacitance optimization for high-speed operation is limited
Solution Approach 1:
The insulating film is configured to divide specific electrode films selectively rather than all electrode films uniformly. This local differentiation allows optimization of resistance and capacitance characteristics in specific memory cells where high-speed operation is critical, while maintaining simpler structures in other areas. The selective division enables tailored electrical characteristics without requiring complete structural redesign throughout the entire device.
3Manufacturing precision
If larger spacing between columnar structures is used, then manufacturing precision requirements are reduced, but the memory cell performance and operational speed decrease
Solution Approach 1:
The patent implements different spacing configurations for different groups of columnar structures. First columnar structures are spaced at a first distance while second columnar structures are spaced at a second distance. This allows memory cells requiring high performance to have tighter spacing for optimized electrical characteristics, while other areas can tolerate larger spacing with relaxed manufacturing precision requirements. The localized optimization achieves high data access speed in critical areas without imposing stringent precision requirements across the entire device.
Data Source
AI summary
A semiconductor memory device according to one embodiment, includes a stacked body including a plurality of electrode films stacked separated from each other along a first direction, a plurality of columnar structures extending in the first direction, piercing the stacked body, and including a semiconductor layer, a charge storage film provided between one of the columnar structures and the electrode films, and an insulating film dividing one of the electrode films disposed in an upper portion of the stacked body and not dividing other one of the electrode films disposed in a lower portion of the stacked body. A shortest distance between the columnar structures disposed on one side of the insulating film being shorter than a shortest distance between the columnar structures disposed with the insulating film interposed between the columnar structures.