Memory Device Column Plane Testing Encoder
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Solution Overview
Problem
Conventional methods for testing memory devices are time-consuming and resource-intensive, as they require sequentially testing each column plane to detect defective columns, leading to high data transfer volumes and inefficient identification of defective column planes.
Innovation Solution
The implementation of an encoder within the memory device that receives and encodes test data from multiple column planes simultaneously, reducing the data output to identify defective column planes and facilitate faster testing by generating encoded signals indicative of column plane status.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional sequential testing methods are used for each column plane, then testing completeness is ensured, but testing time and data transfer volume increase significantly
Solution Approach 1:
The patent combines multiple column plane tests into a single parallel testing operation. Multiple column planes are tested simultaneously using shared test circuits and data paths, merging what were previously sequential operations into concurrent processes. This reduces total testing time while maintaining complete coverage of all column planes through coordinated test signal distribution and response collection.
Solution Approach 2:
The patent implements dynamic test circuit configuration where test circuits can be dynamically allocated and shared across multiple column planes during parallel testing. The system dynamically routes test signals and collects responses from multiple column planes through reconfigurable data paths, enabling flexible parallel operation without requiring dedicated static circuits for each column plane.
2Measurement precision
If conventional sequential testing methods are used for each column plane, then testing accuracy is maintained, but data transfer volume and resource consumption increase
Solution Approach 1:
The patent extracts and processes test data from multiple column planes simultaneously, collecting responses in parallel rather than sequentially. By extracting data from all tested column planes at once through shared data paths and processing circuits, the system reduces the cumulative data transfer volume that would result from multiple sequential transfers, while maintaining complete and accurate data collection for each column plane.
3Productivity
If encoder is implemented to encode test data from multiple column planes, then testing efficiency increases, but device complexity increases
Solution Approach 1:
The encoder implemented in the patent is designed as a universal circuit that can handle test data from multiple column planes through a standardized interface. This multi-functional encoder processes encoded data regardless of which specific column planes are being tested, reducing the need for separate encoding circuits for each column plane and thereby limiting the increase in device complexity while maintaining high testing efficiency.
Data Source
AI summary
Memory devices are disclosed. A memory device may include a memory array including a number of column planes and at least one circuit coupled to the memory array. The at least one circuit may generate test result data for a column address for each column plane of the number of column planes. The at least one circuit may further convert the test result data to a first result responsive to two or more of the column planes failing the test. The at least one circuit may also convert the test result data to a second result responsive to no column planes failing the test. Further, the at least one circuit may convert the test result data to a third result responsive to one column plane failing the test. The third result may identify the one column plane. Methods of testing a memory device, and electronic systems are also disclosed.