3D Memory Columnar Body Diameter Variation Compensation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in maintaining consistent characteristics and integration levels due to variations in the internal and external diameters of memory columnar bodies, which affect the performance and reliability of memory cells.
Innovation Solution
A manufacturing method involving the alternating stacking of inter-layer insulating and sacrificial layers, forming openings with varying internal diameters, and using a cover insulating layer with thickness variations to match the internal diameter changes, ensuring uniformity and stability of the memory cell structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the internal diameter of the opening is made smaller downwardly to match diameter variations, then manufacturing precision of memory columnar bodies is improved, but device complexity increases due to requiring variable thickness cover insulating layers
Solution Approach 1:
The cover insulating layer is designed with locally varying thickness to match the local diameter variations of the memory columnar bodies. The thickness is smaller in lower portions where diameter variation is greater and larger in upper portions where diameter variation is smaller, providing targeted compensation at each location.
Solution Approach 2:
The thickness parameter of the cover insulating layer is changed to compensate for diameter variations. By adjusting the thickness parameter locally, the external diameter of the memory columnar bodies is maintained within a consistent range despite internal diameter variations.
2Productivity
If three-dimensional memory structure is implemented to raise integration level, then productivity is improved, but manufacturing precision becomes more difficult to maintain due to variations in columnar body dimensions
Solution Approach 1:
The patent transitions from planar memory structure to three-dimensional stacked structure with memory columnar bodies extending vertically. Multiple memory cells are arranged in three dimensions, significantly increasing integration level and storage capacity.
Solution Approach 2:
The cover insulating layer thickness is locally optimized at different heights and positions to compensate for position-dependent diameter variations in the memory columnar bodies, ensuring consistent memory cell characteristics throughout the three-dimensional structure.
Data Source
AI summary
Manufactured in a method of manufacturing according to an embodiment is a semiconductor memory device including: control gate electrodes; a semiconductor layer; and a charge accumulation layer. In this method of manufacturing, inter-layer insulating layers and sacrifice layers are stacked alternately, an opening that penetrates the inter-layer insulating layers and sacrifice layers is formed, a first insulating layer, the charge accumulation layer, and the semiconductor layer are formed in the opening, the sacrifice layer and part of the first insulating layer are removed, and the control gate electrodes are formed. An internal diameter of the opening is smaller the more downwardly a portion of the opening is positioned. A film thickness of the first insulating layer is smaller the more downwardly a portion of the first insulating layer is positioned.