Memory Error Correction Using Combinational Decoding Circuits

Solution Overview

Problem

Existing memory systems rely on resource-intensive iterative algorithms using sequential circuits for error correction, which increase power consumption, reduce performance, and limit accuracy.

Innovation Solution

Implementing error control in memory systems using combinational logic, specifically through the use of combinational circuits for encoding and decoding data packets with DSC error correction schemes, reducing reliance on sequential circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If iterative algorithms using sequential circuits are used for error correction, then error correction capability is achieved, but power consumption increases and performance decreases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent replaces sequential circuit-based iterative algorithms with combinational circuit-based algebraic algorithms. This substitution fundamentally changes the computational approach from time-sequential operations to parallel combinational logic operations, thereby reducing power consumption while maintaining error correction capability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the algorithmic parameters by transitioning from iterative methods to closed-form algebraic solutions. This parameter change in the computational approach eliminates the need for repeated iterations, directly reducing the energy required for error correction operations.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If iterative algorithms using sequential circuits are used for error correction, then error correction capability is achieved, but performance is reduced

Engineering Contradiction:

Improveerror correction capabilityVSAvoidperformance

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent replaces sequential circuit-based iterative algorithms with combinational circuit-based algebraic algorithms. This substitution fundamentally changes the computational approach from time-sequential operations to parallel combinational logic operations, thereby reducing power consumption while maintaining error correction capability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If iterative algorithms using sequential circuits are used for error correction, then error correction capability is achieved, but processing circuitry complexity increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidprocessing circuitry complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces sequential circuit-based iterative algorithms with combinational circuit-based algebraic algorithms. This substitution fundamentally changes the computational approach from time-sequential operations to parallel combinational logic operations, thereby reducing power consumption while maintaining error correction capability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12585408B2Error control in memory systems using combinational circuits

Publication Date: 2026.03.24 MICRON TECHNOLOGY INC

AI summary

In some implementations, a memory system may obtain, from a host system, a command to read data. The memory system may retrieve a codeword associated with the data. The memory system may generate, based on the codeword, a syndrome. The memory system may generate one or more decoding values based on the syndrome and using one or more combinational circuits. The memory system may correct one or more errors in the codeword using the one or more decoding values. The memory system may provide the data to the host system.