Memory Sub-System Combined Read Process for Soft and Hard Bits
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Solution Overview
Problem
Conventional memory systems face inefficiencies in reading data due to shifts in threshold voltages of memory cells, leading to high bit error rates and increased latency in error detection and recovery, particularly when storing multiple bits of data, as they require multiple rounds of calibration and retry operations to decode error-free data.
Innovation Solution
Implementing a combined process in memory sub-systems to read both hard bit data and soft bit data using calibrated read voltages and voltages with predetermined offsets, where signal and noise characteristics are measured to optimize read voltages and minimize delay by scheduling the reading of both data types together, and selectively transmitting soft bit data based on error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple rounds of calibration and retry operations are performed to decode error-free data, then error recovery capability is improved, but latency increases
Solution Approach 1:
The patent applies preliminary action by performing calibration and reading both hard bit data and soft bit data in advance, before error detection is needed. The soft bit data is read simultaneously with hard bit data using calibrated read voltages, so when errors are detected in hard bit data, the soft bit data is already available for immediate error recovery without requiring additional latency for retry operations.
2Measurement precision
If separate read commands are used for hard bit data and soft bit data, then error detection accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the reading operations for hard bit data and soft bit data into a single combined read command. The memory device receives one read command that triggers simultaneous reading of both data types using calibrated read voltages, eliminating the need for separate read commands while maintaining error detection accuracy through the combined process.
3Reliability
If soft bit data is always transmitted, then error recovery capability is improved, but data transmission overhead increases
Solution Approach 1:
The patent applies local quality by selectively transmitting soft bit data based on the specific needs of each read operation. The system transmits soft bit data only when error detection indicates it is needed for error recovery, rather than always transmitting it. This conditional transmission maintains error recovery capability while minimizing unnecessary data transmission overhead.
Data Source
AI summary
A memory sub-system configured to execute a read command of a first type using a combine process to read soft bit data and hard bit data from memory cells. For example, a memory device is to: measure signal and noise characteristics of memory cells for the read command; calculate, based on the characteristics, an optimized voltage and two adjacent voltages that have offsets of a same amount from the optimized voltage; read the memory cells for hard bit data using the optimized voltage and for soft bit data using the two adjacent voltages; and transmit, to the processing device, a response including the hard bit data. The soft bit data can be selectively transmitted based on a classification determined from the characteristics. When a read command of a second type is executed, soft bit data is not read; and/or the signal and noise characteristics are not measured.