Memory Command/Address Calibration for High-Rate Signal Integrity
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Solution Overview
Problem
In memory systems, particularly DRAM systems, signal integrity is degraded due to propagation delays and variations in signal skew between data, command, and clock signals, which are exacerbated by factors like interconnection capacitors and parasitic capacitances, especially at higher data rates.
Innovation Solution
A method of command/address calibration is employed, involving the transmission of multiple test signals at varying phases relative to a clock signal, followed by comparison and determination of an optimal phase alignment to improve signal timing accuracy and integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data rate of DRAM is increased, then productivity is improved, but signal integrity deteriorates due to propagation delays and signal skew
Solution Approach 1:
The patent performs command/address calibration before normal memory operations to pre-establish optimal timing parameters. The calibration process sends test commands at various phases and determines the optimal phase alignment between command/address signals and clock signals, storing these calibration results for use during high-speed operations to maintain signal integrity at increased data rates
Solution Approach 2:
The patent dynamically adjusts the phase of command/address signals relative to the clock signal based on calibration results. By changing the timing parameter (phase alignment) of signals, the system optimizes signal integrity for different operating conditions and maintains reliable communication even at higher data rates where propagation delays become more significant
2Measurement precision
If propagation delay compensation is implemented through multiple phase testing, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent uses the existing command/address bus and data bus for calibration purposes, making these existing structures serve multiple functions (normal operation and calibration). The calibration commands are transmitted using the same command/address bus infrastructure, and results are received through the data bus, avoiding the need for dedicated calibration hardware and reducing overall device complexity
Solution Approach 2:
The calibration process is self-performing, where the memory device calibrates its own timing parameters using its existing signal paths and logic. The device sends test commands, receives echoed-back test commands, and determines optimal phase alignment internally without requiring external calibration equipment or complex additional circuitry
Data Source
AI summary
During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.