Memory Command Aggregation for Sequential NAND Throughput
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Solution Overview
Problem
The existing memory command processing methods result in significant processing overhead and reduced throughput due to the amplification of host memory commands into multiple NAND memory commands, which require separate processing and time to complete for each access in memory devices like NAND memory devices.
Innovation Solution
The aggregation of NAND read memory commands into a single aggregated command, allowing multiple physical block addresses to be combined into a single command if they are within the same channel, die, and page, reducing the number of commands sent to the memory device and processing time, while ensuring data is returned without excess delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If host memory commands are translated into multiple NAND memory commands, then data access capability is improved, but processing overhead increases and throughput decreases
Solution Approach 1:
The patent combines multiple individual NAND memory commands into a single aggregated command that can access multiple physical block addresses. Instead of translating each host memory command into separate NAND commands, the system aggregates these commands and translates them into one unified command structure, reducing the total number of commands processed by the memory device while maintaining the same data access capability.
2Measurement precision
If multiple separate NAND commands are sent to the memory device, then precise data access is achieved, but the number of commands increases and processing time extends
Solution Approach 1:
The patent merges multiple precise data access operations into a single aggregated command that preserves the precision of individual accesses while executing them in parallel or sequential batches. The aggregated command structure includes multiple physical block addresses, allowing the memory device to process multiple precise access requests simultaneously, thereby reducing total processing time without sacrificing access precision.
Solution Approach 2:
The system performs preliminary aggregation of multiple NAND memory commands into a single command before transmission to the memory device. This preliminary action consolidates the command stream, allowing the memory device to receive and process fewer commands with less overhead, thereby reducing the time lost to command processing while maintaining precise data access capability.
3Reliability
If sequential memory commands are processed individually, then command processing accuracy is maintained, but throughput is reduced
Solution Approach 1:
The patent merges sequential memory commands into an aggregated command structure that maintains the integrity and accuracy of each individual command while enabling batch processing. The aggregated command preserves all necessary address and control information for each underlying operation, ensuring that command processing accuracy is maintained even as throughput increases through reduced command overhead and parallel execution capability.
Data Source
AI summary
A method is described, which includes receiving, by a memory subsystem controller from a host system, a host read memory command that references a set of logical block addresses associated with a set of transfer units of a memory device. The controller converts the set of logical block addresses to a set of physical block addresses for the set of transfer units; generates a set of device read memory commands based on the physical block addresses, wherein each device read memory command references at least one physical block address; and generates a first aggregated device read memory command based on a first device read memory command and a second read memory command in response to determining that the first device read memory command is associated with the second device read memory command. The controller thereafter transmits the first aggregated device read memory command to the memory device.