Memory Subsystem Command Batching via Linked List
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Solution Overview
Problem
In memory sub-systems, submitting and processing individual write commands serially can lead to inefficiencies, particularly when dealing with write commands across page or multi-page boundaries, resulting in increased latency and performance loss due to higher signaling and processing overhead.
Innovation Solution
Implementing command batching by generating a linked list of transfer units with pointers, where an indicator is sent to the processing core, allowing retrieval of transfer units from shared memory, reducing the number of messages and processing time for write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If individual write commands are submitted and processed serially, then command processing simplicity is maintained, but processing time and latency increase
Solution Approach 1:
The patent implements command batching where multiple write commands are collected and prepared in advance before being processed together. The cursor receives and queues multiple write commands, then processes them in a single batch operation, performing the preparatory work of command collection before the actual processing occurs.
Solution Approach 2:
The patent merges multiple individual write commands into a single batched command structure. Instead of processing commands one at a time, the system combines multiple write operations targeting the same block into one unified processing event, reducing the total number of processing cycles required.
2Productivity
If multiple individual write commands are processed, then data writing completeness is ensured, but signaling overhead and performance increase
Solution Approach 1:
The patent combines multiple write commands into a single batched operation, merging the signaling events into one consolidated command sequence. This reduces the number of individual signaling transactions between the host and memory device, lowering the overall signaling overhead and energy consumption.
Solution Approach 2:
The system performs preliminary batching of write commands before transmission to the memory device. By preparing and organizing multiple write operations into a batch structure in advance, the system reduces the frequency of signaling events during actual data writing operations.
3Productivity
If write commands are processed across page boundaries individually, then address precision is maintained, but processing efficiency decreases
Solution Approach 1:
The patent merges multiple write commands that span page boundaries into a single batched processing operation. By treating adjacent pages as a unified processing unit within the batch, the system maintains precise address targeting while improving overall processing efficiency through reduced command overhead.
Solution Approach 2:
The cursor performs preliminary organization of write commands in the batch, ensuring that commands targeting specific addresses and pages are properly sequenced and grouped before processing. This preliminary arrangement maintains address precision while enabling more efficient batch execution.
Data Source
AI summary
Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.