Multiplexed Memory Command Bus for Stable NVDIMM Impedance
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Solution Overview
Problem
NVDIMMs face challenges in maintaining predictable electrical impedance on the command/address bus due to the inclusion of a command/address multiplexer, especially as memory capacity increases, which complicates compatibility with both host devices and onboard controllers.
Innovation Solution
Implementing a multiplexed command/address bus system that routes command/address signals through both a registering clock driver and a controller, allowing for predictable electrical load matching and improved signal integrity by driving signals at levels specified by the volatile memory design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a command/address multiplexer is added to NVDIMM to handle additional tasks, then the functionality and versatility of the memory module is improved, but the electrical impedance predictability on the command/address bus deteriorates
Solution Approach 1:
The patent introduces a buffer as an intermediary component between the multiplexer and the command/address bus. This buffer acts as a mediator that isolates the impedance variations introduced by the multiplexer from the bus, thereby maintaining impedance predictability while allowing the multiplexer to provide enhanced functionality for handling both volatile and non-volatile memory operations.
2Quantity of substance
If memory capacity is increased in NVDIMM, then the storage capability is improved, but the device complexity and difficulty of maintaining electrical characteristics deteriorates
Solution Approach 1:
The patent segments the memory system into distinct volatile and non-volatile memory portions, each with their own control logic and interfaces. This segmentation allows independent optimization of each memory type while managing overall complexity through modular architecture, enabling increased total capacity without proportionally increasing system complexity.
Solution Approach 2:
The buffer serves as an intermediary that simplifies the interface between the complex multiplexer and the command/address bus, thereby reducing the overall device complexity despite increased memory capacity and additional functionality.
3Adaptability or versatility
If a command/address multiplexer is added to NVDIMM, then the versatility for handling multiple memory types is improved, but the difficulty of detecting and measuring electrical characteristics deteriorates
Solution Approach 1:
The buffer acts as a measurement-friendly intermediary that provides a stable, predictable interface between the multiplexer and the command/address bus. This isolation makes it easier to detect and measure electrical characteristics on the bus side, as the buffer absorbs the variability introduced by the multiplexer's switching between different memory types.
Data Source
AI summary
A memory device includes a first plurality of volatile memories, a non-volatile memory, and a controller coupled to the non-volatile memory and including a first controller output. The memory device further includes a registering clock driver (RCD) including a first RCD output, and a first multiplexer including a first mux input coupled to the first RCD output, a second mux input coupled to the first controller output, and a first mux output coupled to the first plurality of volatile memories. The first multiplexer can be configured to provide command/address signals from one of the RCD and the controller to the first plurality of volatile memories.