Memory Command Alignment Using a Multiplied Reference Clock
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Solution Overview
Problem
Integrated circuits face performance asymmetry due to disparate circuit technologies for I/O circuitry and memory cells, leading to difficulties in optimizing overall device performance as I/O speed outpaces memory core capabilities.
Innovation Solution
A memory system design that uses a reference clock signal to align command signals, allowing for reduced timing constraints in command decoding by serializing and deserializing signals at different frequencies, enabling efficient communication between memory controller and device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If I/O circuitry speed is increased to reduce the number of command, address, and data lines, then the number of lines is reduced, but the memory device may have trouble processing commands as fast as the I/O circuitry is capable of delivering them
Solution Approach 1:
The patent implements dynamic frequency multiplication where the command sampling clock frequency is multiplied relative to the I/O clock frequency. This allows the system to adaptively handle the speed mismatch between fast I/O circuitry and slower memory core, enabling the I/O to operate at higher speeds while the memory core processes commands at its native speed through asynchronous operation and buffer management.
2Productivity
If I/O speed performance increases faster than memory core, then fewer lines are required, but performance asymmetry complicates optimization of overall device performance
Solution Approach 1:
The patent introduces command buffers and timing control logic as intermediary components between the high-speed I/O circuitry and the slower memory core. These intermediaries absorb the performance asymmetry by buffering commands received at high speed and delivering them to the memory core at its processing rate, thereby decoupling the two subsystems and allowing independent optimization.
3Quantity of substance
If command signals are serialized at high bit rates, then fewer lines are needed, but timing constraints for command decoding become more stringent
Solution Approach 1:
The patent changes the timing parameters by using frequency multiplication to generate a command sampling clock at a higher frequency than the I/O clock. This parameter change allows the system to meet stringent timing requirements by sampling commands at multiple points within each I/O clock period, thereby relaxing the effective timing constraints despite high serialization rates.
Data Source
AI summary
A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock signal to develop a command-recovery clock signal with which to sample the incoming command signals. The memory controller issues the command signals as a series of multi-bit command words aligned with edges of the reference-clock signal so that the memory device can use edges of the reference clock signal for command-word alignment.