Memory Command Verification for Decoding and Execution Errors
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Solution Overview
Problem
Existing memory systems face challenges in detecting errors associated with decoding and executing commands in memory devices, which can negatively affect system reliability, particularly in applications with high reliability constraints such as automotive vehicles with autonomous or semi-autonomous driving capabilities.
Innovation Solution
Implementing techniques for memory command verification that compare the access instruction and address included in the command to the executed access instruction and execution address to detect errors, allowing for retransmission of improperly executed commands and enhancing system reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory command verification is implemented to detect decoding and execution errors, then system reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements preliminary verification by capturing the command at the input buffer before decoding occurs. This allows the verification component to have a reference copy of the original command for later comparison with the decoded command, enabling error detection without adding complex real-time monitoring mechanisms.
Solution Approach 2:
The patent introduces a verification component as an intermediary between the decoder and the command execution pipeline. This component compares the captured command with the decoded command and generates verification signals, acting as a mediator that detects errors without directly interfering with the core decoding and execution functions.
2Measurement precision
If command verification and error detection mechanisms are added, then command execution accuracy is improved, but processing time increases
Solution Approach 1:
The command is captured at the input buffer stage before decoding, creating a reference copy in advance. This preliminary action allows the verification process to simply compare two existing commands rather than performing complex analysis during execution, minimizing time loss.
Solution Approach 2:
The verification process skips detailed analysis of correct commands by using direct comparison of captured and decoded commands. Only when discrepancies are detected does the system engage in further error handling, allowing most commands to pass through verification quickly without significant time penalty.
Data Source
AI summary
Methods, systems, and devices for performing memory command verification are described. A system may include a memory device and a memory controller, which may be external (e.g., a host device). The memory device may receive, from the memory controller, a command indicating a type of operation and an address. The memory device may decode the command and execute an operation (e.g., the operation corresponding to the decoded command) at an execution location on the memory device. The system (e.g., the memory device or the memory controller) may determine whether the executed operation and execution location match the type of operation and address indicated in the command, and the system may thereby determine an error associated with the decoding, the execution, or both of the command.