Memory Access Command Delay Circuit for Clock Domain Alignment
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Solution Overview
Problem
Existing memory systems face challenges in aligning access commands with the correct timing due to differences between clock domains, particularly in three-dimensional memory arrays, leading to difficulties in synchronizing data transfer between storage and device time domains.
Innovation Solution
Implementing a delay locked loop (DLL) circuitry to align access commands, such as write commands, by subjecting them to the same delays as a reference clock signal, ensuring proper timing alignment with data strobe signals through a delay line and clock tree circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If access commands are transmitted without delay adjustment, then device complexity is reduced, but timing alignment between clock domains deteriorates
Solution Approach 1:
A delay locked loop (DLL) circuit is introduced as an intermediary component between the command interface and memory array. The DLL receives the access command and introduces a controllable delay to align it with the reference clock timing, thereby resolving the timing mismatch between clock domains without requiring fundamental changes to the memory architecture.
Solution Approach 2:
The delay adjustment is performed in advance before the access command is latched and processed. The DLL circuit pre-delays the command signal based on measured timing differences, ensuring that by the time the command reaches the memory array, it is already synchronized with the reference clock domain.
2Manufacturing precision
If delay locked loop circuitry is added to align access commands, then timing alignment improves, but device complexity increases
Solution Approach 1:
The DLL circuit incorporates feedback mechanisms that monitor the timing relationship between the access command and reference clock, and automatically adjust the delay amount to maintain optimal alignment. This feedback control enables precise timing synchronization while keeping the delay adjustment automatic rather than requiring manual calibration.
Solution Approach 2:
The delay amount in the DLL circuit is made dynamic and adjustable rather than fixed. The circuit can adapt the delay value based on operating conditions, temperature, and measured timing differences, allowing precise timing alignment to be maintained across varying conditions without requiring multiple fixed delay circuits.
Data Source
AI summary
Memory devices may have a memory array and a command delay circuit that adjusts signals associated with operations to access of the memory array. The memory device may also include a controller that delays an access command to access the memory array by transmitting the access command through delay circuitry of the command delay circuitry. This may cause the access command to be delayed by a first duration of time when output from the delay circuitry. Delay of the access command may align a data signal and the access command such that the access command and a system clock may cause latching of suitable data of the data signal.