Memory Command Synchronization Using DLL Clock Enable Control
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Solution Overview
Problem
High-frequency clock signals in memory devices complicate the synchronization of internal command and clock signals, leading to potential errors in data reading and writing, especially in multi-data rate memories, and existing solutions increase power consumption.
Innovation Solution
The implementation of a control circuit with a delay locked loop (DLL) and read/write dQ-Enable-Delay (R/W QED) circuit synchronizes delayed command read/write signals with an internal clock signal, using adjustable latency values to ensure proper timing across different clock periods, reducing power consumption through DLL clock enable control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional circuits are provided for command and clock synchronization, then synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic control of the DLL clock enable signal based on command type. The control circuit dynamically adjusts whether to enable the DLL clock for read commands versus write commands, allowing the system to adapt power consumption to actual operational needs while maintaining synchronization accuracy when required
Solution Approach 2:
The patent changes the operational parameters of the DLL by selectively enabling or disabling its clock signal based on command type. This parameter change allows the system to reduce power consumption during operations where full DLL functionality is not required, while maintaining synchronization capability when needed
2Productivity
If higher frequency clock signals are used, then data transfer rate is improved, but synchronization difficulty increases
Solution Approach 1:
The patent introduces a control circuit as an intermediary between the command input and the DLL. This control circuit processes command signals and generates appropriate DLL clock enable signals, simplifying the synchronization task by mediating between the high-frequency clock system and the command execution requirements
Solution Approach 2:
The system uses feedback from command type detection to control DLL clock enabling. The control circuit monitors incoming commands and provides feedback control to the DLL clock enable signal, allowing automatic adjustment of synchronization behavior based on operational requirements without increasing system complexity
3Reliability
If DLL clock is continuously enabled, then synchronization reliability is improved, but power consumption increases
Solution Approach 1:
Instead of continuous DLL clock enabling, the patent implements periodic or conditional enabling based on command type. The DLL clock is enabled only during specific command operations (differentiating between read and write commands), creating a periodic action pattern that maintains reliability when needed while reducing overall power consumption
Data Source
AI summary
An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.