Memory Command Synchronization Using DLL and Variable Latency
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Solution Overview
Problem
High-frequency clock signals in memory devices complicate the synchronization of internal command and clock signals, leading to potential misinterpretation of commands and incorrect data transfer, especially in multi-data rate memories, where accurate timing is crucial to prevent errors and increase power consumption.
Innovation Solution
The implementation of a control circuit with a delay locked loop (DLL) and read/write dQ-Enable-Delay (R/W QED) circuit synchronizes delayed command read/write signals with an internal clock signal, using CAS latency and write latency signals to adjust timing, allowing for multiple modes of operation (3T, 2T, and 1T) to accommodate varying clock periods and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional circuitry is provided for command and clock synchronization, then synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic synchronization modes (1T, 2T, 3T) that adjust the timing relationship between command signals and internal clock signals based on operating conditions. The system can switch between different latency values (1 clock period, 2 clock periods, or 3 clock periods) to optimize both synchronization accuracy and power consumption for different memory operations and clock frequencies.
Solution Approach 2:
The patent changes the timing parameter (latency) between command signals and internal clock signals to resolve the contradiction. By providing multiple latency options (1T, 2T, 3T modes), the system can select the appropriate timing relationship based on the specific operation, achieving accurate synchronization while minimizing power consumption by avoiding unnecessary waiting cycles.
2Productivity
If higher clock frequencies are used, then data transfer rate is improved, but timing synchronization becomes more difficult
Solution Approach 1:
The patent applies preliminary action by providing multiple pre-configured synchronization modes (1T, 2T, 3T) that are prepared in advance. The memory device can select the appropriate mode based on the operating clock frequency and operation type, avoiding the need for complex real-time timing adjustments during high-frequency operations.
Solution Approach 2:
The system dynamically adapts to different clock frequencies by selecting from multiple synchronization modes. The timing relationship between command signals and internal clock signals can be adjusted on-the-fly based on the actual operating conditions, enabling the system to maintain accurate synchronization even at high clock frequencies up to 1 GHz and above.
3Adaptability or versatility
If latency is increased to accommodate different clock frequencies, then compatibility is improved, but response time increases
Solution Approach 1:
The patent implements dynamic latency adjustment with multiple operational modes (1T, 2T, 3T) that allow the system to adapt to different clock frequencies while minimizing response time. The controller and memory device can select the shortest appropriate latency based on the specific operation and frequency, achieving both compatibility and fast response.
Solution Approach 2:
The system changes the latency parameter dynamically based on operating conditions. By providing multiple latency options (1 clock period, 2 clock periods, or 3 clock periods), the system can optimize the balance between compatibility with different clock frequencies and minimizing response time for each specific operation.
Data Source
AI summary
An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.