Memory Command Encoding for Single-Cycle Termination Impedance
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in preventing stray voltages from being reflected at terminals during read and write operations, particularly when multiple memory devices share the same data bus, leading to increased latency due to the use of chip select signals for determining target devices.
Innovation Solution
The solution involves setting on-die termination impedance based on encoding bits within access commands received via command/address pins, allowing memory devices to determine their status as targets or non-targets in a single cycle, thereby reducing latency and optimizing impedance matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chip select signals are used to determine target memory devices, then multiple memory devices can share the same data bus, but latency increases due to the additional signal cycle required
Solution Approach 1:
The patent extracts the target device identification function from the chip select signal mechanism and implements it directly within the command structure through encoding bits. This removes the need for separate chip select signaling cycles, allowing memory devices to determine their target status immediately upon receiving the command, thereby eliminating the additional latency while preserving multi-device bus sharing capability
Solution Approach 2:
The patent incorporates encoding bits within the command itself that preliminarily identify the target memory device before the command execution begins. This preliminary identification embedded in the command structure allows devices to self-determine target status without waiting for external chip select signals, reducing the overall operational cycle time
2Device complexity
If termination impedance is not properly matched, then device complexity is reduced, but voltage reflections occur at terminals causing signal integrity issues
Solution Approach 1:
The patent implements local quality by providing multiple selectable termination resistor configurations (e.g., different resistance values and connection topologies) that can be selectively activated based on the specific operational context. This allows each memory device to optimize its terminal impedance locally to match the data bus characteristics, preventing voltage reflections while maintaining manageable device complexity through selective activation rather than permanent complex circuitry
Solution Approach 2:
The patent introduces dynamic termination impedance adjustment by allowing the termination resistance to be changed based on operational mode and target device status. The memory device can dynamically select appropriate termination configurations during different phases of operation (e.g., when identified as target versus non-target device), enabling adaptive impedance matching that prevents reflections without requiring permanently complex circuit architecture
Data Source
AI summary
Apparatuses, systems, and methods for setting termination impedance based on encoding bits are disclosed. A memory receives an access command including one or more encoding bits, which may be received via one or more CA pins. Based on the one or more encoding bits and a setting in a mode register, the memory determines whether it is a target of the access command, and the memory applies a termination impedance based at least in part on the determination of whether it is the target of the access command. In various embodiments, the determination of whether the memory is the target can be performed in a single cycle.