Semiconductor Memory Read Write Command Latency Shifting
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Solution Overview
Problem
DDR synchronous semiconductor memory devices face challenges in meeting data access speed requirements due to limitations in additive latency (AL) and cas latency (CL), particularly during read to write command executions, where the address transfer path differences between read and write commands can lead to errors and incomplete data transfer.
Innovation Solution
The semiconductor memory device incorporates a read command AL shifting unit, a write command AL shifting unit, and a write command CL shifting unit to generate and synchronize shifted commands and address control signals, ensuring the address control signal remains active for a predetermined period, even if the read command is activated later than the write command, thereby maintaining the write address shifting clock active and ensuring reliable address transfer during read to write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the address transfer path for read and write commands is optimized for speed, then data access speed is improved, but errors occur during read to write command executions due to timing mismatches
Solution Approach 1:
The patent applies preliminary action by maintaining the write address control signal in an active state in advance before the read command is fully processed. This ensures that the write address path is prepared and ready, preventing timing conflicts when transitioning from read to write operations. The address control signal is kept active during the read command execution to ensure subsequent write operations can proceed without errors.
2Productivity
If the additive latency and cas latency are reduced to increase data access speed, then productivity is improved, but the address transfer timing becomes mismatched leading to execution errors
Solution Approach 1:
The patent applies dynamics by making the write address control signal dynamically maintainable during read operations. Instead of fixed timing constraints, the system allows the address control signal to remain active throughout the read command execution period, providing flexible timing that accommodates both fast data access and precise address transfer requirements without errors.
3Device complexity
If the address control signal is deactivated immediately after read command activation, then device complexity is reduced, but the write address shifting clock becomes inactive causing transfer errors
Solution Approach 1:
The patent applies continuity of useful action by maintaining the write address control signal in an active state continuously during the read command execution. This continuous active state ensures that the write address shifting clock remains operational, allowing seamless transition from read to write operations without interruption or transfer errors, while maintaining relatively simple control logic.
Data Source
AI summary
A read command AL shifting unit shifts a read command for a predetermined additive latency, to output a shifted read command. A write command AL shifting unit shifts a write command for the predetermined additive latency to output a first shifted write command. A write command CL shifting unit shifts the first shifted write command for a predetermined cas latency to output a second shifted write command. A write address controller generates an address control signal in response to the shifted read command and the first shifted write command. An address transfer circuit transfers an address in response to the address control signal. Other embodiments are also described.