Memory Command Parity Check Using Repurposed Address Bits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory devices, particularly those conforming to low power (LP) standards, lack effective error checking on command and address inputs due to limited provisions for dedicated parity checking, which can lead to errors in high-speed applications.
Innovation Solution
Repurpose existing command pins in memory devices for parity checking by configuring switchable parameter bits as parity bits, enabling efficient parity checks without the need for additional dedicated pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated parity checking pins are added to memory devices, then error detection capability is improved, but device complexity and pin count increase
Solution Approach 1:
The patent applies multi-functionality by enabling command pins to serve dual purposes: transmitting command signals during normal operation and carrying parity check bits during error detection mode. This is achieved through mode register configuration that dynamically assigns parity function to available command pins, eliminating the need for dedicated parity pins while maintaining error detection capability.
2Reliability
If command pins are repurposed for parity checking, then error detection capability is improved, but command signaling capability is reduced
Solution Approach 1:
The patent implements dynamic reconfiguration of pin functionality through mode register settings. The same command pins can be dynamically assigned to different functions (command signaling or parity checking) based on operational mode, allowing the system to adapt between high-speed command operation and error detection modes without hardware changes.
Solution Approach 2:
The patent changes the operational parameters of command pins by modifying their function through mode register configuration. Bits that would normally carry command information are reconfigured to carry parity check information, changing the parameter being transmitted on the same physical pin without requiring additional pins.
3Reliability
If switchable parameter bits are used as parity bits, then diagnostic coverage is improved, but configuration flexibility is reduced
Solution Approach 1:
The patent uses dynamic reconfiguration through mode register settings to assign switchable parameter bits to parity functions only when needed for error detection. During normal operation, these bits maintain their original command signaling function, providing full configuration flexibility while enabling enhanced diagnostic coverage when required.
Data Source
AI summary
In some implementations, a memory device may receive a mode register command that configures a parameter in a mode register of the memory device. The memory device may receive a set of command bits that indicates a command, where configuration of the parameter in the mode register frees a switchable parameter bit, of the set of command bits, that otherwise is used to configure the parameter, and where the switchable parameter bit is used as a parity bit relating to remaining bits of the set of command bits. The memory device may perform a parity check using the switchable parameter bit that is used as the parity bit.