Memory Command Parity Check for High-Coverage Address Verification
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Solution Overview
Problem
Existing memory devices, particularly those conforming to low power standards, have limited provisions for effective error checking on command and address inputs, resulting in diagnostic coverage below 99%, which is insufficient for applications requiring stringent error detection, such as autonomous vehicles.
Innovation Solution
Implementing a separate parity check command that uses additional parity bits to verify the validity of command and address inputs, allowing for increased diagnostic coverage by decreasing the number of command and address bits covered by each parity bit and omitting parity bits from conventional commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional commands include parity bits for error checking, then error detection capability is improved, but command capacity and data capacity are reduced
Solution Approach 1:
The error checking function is segmented from conventional commands into a separate parity check command. This allows conventional commands to maintain full capacity for data transmission while the dedicated parity check command handles error detection, eliminating the need to embed parity bits within each conventional command.
Solution Approach 2:
The separate parity check command structure enables a single command type to be optimized purely for error detection across multiple different conventional commands. This universal error checking mechanism can verify any preceding command without being constrained by the specific data capacity requirements of individual command types.
2Reliability
If additional parity bits are used to increase diagnostic coverage, then error detection reliability is improved, but the number of command and address bits covered by each parity bit decreases
Solution Approach 1:
The parity check functionality is segmented into a separate dedicated command structure, allowing for the implementation of multiple parity bits that can individually cover smaller subsets of command and address bits. This segmentation enables achieving 99% diagnostic coverage by using several parity bits, each monitoring specific bit positions, rather than relying on fewer parity bits covering larger portions.
3Reliability
If parity check is implemented in memory devices conforming to low power standards, then error detection capability is improved, but power consumption increases
Solution Approach 1:
The parity check operation is implemented as a periodic action triggered by specific low power standard commands rather than continuously. The separate parity check command allows the memory device to perform error checking only when explicitly requested, maintaining compatibility with low power standards by avoiding continuous operation while still providing robust error detection capability when needed.
Data Source
AI summary
In some implementations, a memory device may receive a command. The memory device may receive, subsequent to the command, a parity check command, where the parity check command includes a set of parity bits relating to the command. The memory device may perform a parity check for the command using the set of parity bits.