Memory Command Parity Using Shared Data Pins
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In memory systems, performing parity checking on command/address pins is challenging due to constraints on the number of pins available and varying timing requirements, making it impractical to use a dedicated pin for parity, especially when conveying a single bit of CA parity information.
Innovation Solution
The memory device utilizes data-associated pins such as data mask/invert (DMI), error correction code (ECC), or redundant data strobe (RDQS) pins, which are otherwise unused during command cycles, to convey CA parity information, allowing for parity checking without a dedicated pin, and logs the parity check result in a register.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated pin is used for CA parity checking, then parity checking reliability is improved, but the number of pins required increases
Solution Approach 1:
The patent applies multi-functionality by enabling data-associated pins (DMI, ECC, RDQS) to serve dual purposes: their primary data transfer function and an additional function for conveying CA parity information. This allows the system to achieve reliable parity checking without requiring dedicated parity pins, as the same pins are reused for both data and parity communication during different time intervals
2Quantity of substance
If data-associated pins are used for CA parity conveying, then pin quantity is reduced, but timing constraints become more complex
Solution Approach 1:
The patent applies segmentation by dividing the time interval into distinct segments: one for data transfer and another for parity bit conveying. This temporal segmentation allows the same pin to handle different functions at different times, reducing the total number of pins required while managing timing complexity through structured time division
Solution Approach 2:
The patent implements periodic action by establishing a repeating cycle where data-associated pins alternate between data transfer mode and parity conveying mode. This periodic switching creates predictable timing patterns that simplify the management of complex timing constraints, as the pin function changes occur at regular, predetermined intervals
Data Source
AI summary
Methods, systems, and devices for targeted command/address parity low lift are described. A memory device receives a command (e.g., a write command or a read command) from a host device over a first set of pins and performs data transfer over a second set of pins with the host device according to the command. The memory device exchanges a first parity bit associated with the command with the host device, and generates a second parity bit based on the command. A parity result bit is subsequently generated based, at least in part, on the first parity bit and the second parity bit.