Memory Command Decoding With Partial Frames for Early Bank Activation
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Solution Overview
Problem
Conventional memory access operations in computing systems are slowed by serial processes such as bank activate and read commands, which require multiple processor cycles for CRC processing and decoding, leading to increased latency in distributed memory subsystems.
Innovation Solution
A method to decode and execute memory commands with partial frame data by sending unverified commands to a FIFO unit before CRC completion, allowing early bank activation and verification based on CRC results, reducing latency in distributed memory subsystems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire frame data is received and verified before command execution, then data correctness is ensured through CRC, but memory access latency increases due to waiting for full frame arrival
Solution Approach 1:
The patent applies preliminary action by decoding and queuing memory commands before the complete frame data arrives and before CRC verification is finished. The command decoder extracts opcodes and address bits from incoming frame data and places commands in a command queue in advance, allowing the memory interface to begin processing while verification is still in progress. This reduces latency by performing useful work before all data is available.
Solution Approach 2:
The patent segments the frame data processing into independent components: opcode extraction, address bit collection, CRC verification, and command execution. Each component can be processed independently or in parallel, allowing the system to work on multiple aspects of command processing simultaneously rather than waiting for the entire frame to be received and verified sequentially.
2Reliability
If CRC verification is performed before command decoding, then data integrity is confirmed, but processing cycles are wasted due to serial process sequencing
Solution Approach 1:
The patent introduces dynamic processing where command decoding and queuing operations adapt to the arrival of frame data in real-time. The system dynamically adjusts the ordering of operations based on data availability, allowing decoding to proceed as soon as sufficient data arrives rather than following a fixed serial sequence. This improves productivity by optimizing the processing flow dynamically.
Solution Approach 2:
The patent ensures continuity of useful action by maintaining a pipeline where frame data reception, decoding, queuing, and CRC verification all proceed concurrently rather than in discrete sequential steps. The memory interface continuously processes available data while verification completes, eliminating idle cycles and maintaining productive work throughout the entire frame processing interval.
3Reliability
If bank activation waits for complete frame verification, then command accuracy is ensured, but scheduling efficiency decreases and high-priority commands are delayed
Solution Approach 1:
The patent applies preliminary action by preparing bank activation commands in advance based on decoded information from incoming frames, even before CRC verification completes. The command queue holds pre-decoded commands ready for immediate execution, allowing the memory controller to schedule and initiate bank activations proactively rather than reactively after full verification. This improves scheduling efficiency while maintaining accuracy through subsequent verification.
Data Source
AI summary
A computer-implemented method to decode and execute a memory command with partial frame data is provided. The computer-implemented method includes receiving the memory command during early cycles of a frame, the memory command being locatable in a template of the frame by reference to an opcode of the frame, sending the memory command to a command first-in-first-out (FIFO) unit as an unverified command once decoder logic decodes the memory command, prior to a cyclic redundancy check (CRC) and prior to arrival of full address bits of the frame in later cycles, entering the unverified command into a scheduling queue to allow for early bank activation, executing the CRC and confirming the unverified command as a verified command based on no errors being found during the CRC.