Memory Command Path Delay Alignment Under PVT Variation
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Solution Overview
Problem
High-speed semiconductor memory systems face challenges in maintaining proper timing of internal clock, data, and command signals due to high-frequency memory clock signals and varying propagation delays caused by changes in power, voltage, and temperature, leading to potential operational failures.
Innovation Solution
A timing calibration and adjustment circuit is implemented to align command and data signals with clock signals, using a clock receiver, clock buffer, data receiver, and latency shift circuit to account for propagation delays and ensure correct timing margins, even under changing conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional timing models assume equal propagation delay for clock and data paths, then timing can be maintained under ideal conditions, but power consumption increases due to continuous operation of delays and counter circuitry
Solution Approach 1:
The patent extracts the timing calibration function from continuous operation into a separate calibration phase. The calibration circuit measures and stores delay differences between clock and data paths, then uses this stored information to adjust command timing without requiring continuous active calibration circuitry, thereby reducing power consumption while maintaining timing accuracy.
Solution Approach 2:
The patent performs timing calibration in advance during a calibration phase before normal memory operation. The calibration circuit pre-determines the delay differences between clock and data paths and stores this information, so that during normal operation, the command path can be adjusted using this pre-calibrated information without continuous calibration activity, reducing power consumption while ensuring timing accuracy.
2Reliability
If delay circuitry is added to clock or write command paths to compensate for propagation delay variations, then timing can be maintained, but the variations due to changing operating conditions still negatively affect signal timing
Solution Approach 1:
The patent implements a feedback mechanism where the calibration circuit measures the actual propagation delay differences between clock and data paths under specific operating conditions, stores this measured information, and uses it to adjust the command path timing. This feedback-based approach allows the system to adapt to changing operating conditions (power, voltage, temperature) by using the stored calibration data to compensate for delay variations, improving both timing stability and adaptability.
3Productivity
If multi-data rate memory receives data at twice the clock frequency, then data transfer rate increases, but timing domain crossing becomes more complex requiring precise coordination of command and clock signals
Solution Approach 1:
The patent employs dynamic timing adjustment in the command path based on calibration information. The system dynamically selects appropriate delay values for the command path from multiple available delay stages, allowing the timing to be optimized for different operating modes including multi-data rate operation. This dynamic adjustment capability enables the system to handle the increased timing coordination complexity of multi-data rate operation while maintaining high data transfer rates.
Data Source
AI summary
Command paths, apparatuses, memories, and methods for providing an internal command to a data path are disclosed. In an example method, a command is received and propagated through a command path to provide an internal command. Further included in the method is determining a difference between a latency value and a path delay difference, the path delay difference representing a modeled path delay difference between the command path and the data path measured in terms of a number of clock periods. The propagation of the command through the command path to the data path is delayed by a delay based at least in part on the difference between the latency value and the path delay difference. The internal command is provided to the data path responsive to an internal clock signal.