Memory System Command Processing Unit for Multi-Plane Operation
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Solution Overview
Problem
Current memory systems have complex flash memory interfaces that complicate the control and operation of semiconductor memory devices, particularly in managing commands and status information across multiple planes, leading to inefficiencies in data storage and retrieval operations.
Innovation Solution
A memory system with a simplified flash memory interface is introduced, featuring a command processing unit that generates internal commands based on external commands and uses a status register to store status information, allowing for efficient operation across multiple planes, and an operating method that decodes external commands and generates internal commands for execution, optimizing command queuing and execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a complex flash memory interface is used to manage commands and status information across multiple planes, then the memory system can handle multiple planes, but the controller complexity increases
Solution Approach 1:
The memory device is divided into multiple independent planes, each capable of autonomous operation. Each plane has its own command queue and status register, allowing parallel processing of commands without requiring complex cross-plane coordination in the controller. This segmentation enables multi-plane operation while keeping the controller interface simple.
Solution Approach 2:
The status register is designed to store status information for multiple planes using a unified structure with plane-selectable tags. The same status register can serve multiple planes by selecting different tags, eliminating the need for separate status registers for each plane and reducing controller complexity.
2Loss of information
If separate status registers are used for each plane, then status information can be stored for all planes, but the device complexity increases
Solution Approach 1:
Multiple plane status information is merged into a single status register by using plane-selectable tags. Each tag corresponds to a specific plane, allowing the same status register to store and retrieve status information for any plane. This merging approach maintains complete status information while reducing the number of physical registers needed.
Solution Approach 2:
Tags serve as intermediaries between the single status register and multiple planes. The tags encode plane identification information, allowing the controller to selectively access status information for any plane through the same status register interface, eliminating the need for multiple separate registers.
3Productivity
If multiple command queues are used to manage commands for multiple planes, then command processing efficiency is improved, but the device complexity increases
Solution Approach 1:
The command processing system is segmented into multiple independent command queues, each dedicated to processing commands for specific planes. This allows parallel command processing across different planes without requiring complex arbitration logic, improving throughput while maintaining simple queue structures.
Solution Approach 2:
Commands are pre-queued in plane-specific command queues before execution. This preliminary organization of commands by plane allows the memory device to efficiently batch and process commands for each plane without requiring complex real-time scheduling decisions during execution.
Data Source
AI summary
A semiconductor memory device according to the present disclosure includes: a memory cell array including a plurality of planes; a command processing unit configured to generate an internal command to be executed by at least one plane among the plurality of planes on the basis of external commands received from an external controller; a status register configured to store status information of the external commands by a tag included in the external command according to results of performing the internal command.