Memory Command Re-sequencing for Latency Reduction

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Solution Overview

Problem

In data storage applications, existing techniques for processing sequences of memory commands do not effectively optimize execution order to improve performance, leading to suboptimal latency and interference issues in memory operations.

Innovation Solution

A memory controller identifies situations where executing a second memory command before a first command can improve the performance of the first command, such as by reading lower pages before upper pages or executing commands with reduced interference levels, and modifies the execution order accordingly to cache or calculate thresholds based on the results of the second command.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory commands are executed in the order they appear in the sequence, then command processing simplicity is maintained, but execution performance and latency are suboptimal

Engineering Contradiction:
Improveexecution performanceVSAvoidcommand execution control
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system performs preliminary analysis of the command sequence to identify optimal execution orders before actually executing commands. The controller determines that executing the second command before the first command would improve performance, and prepares the execution plan accordingly, caching lower pages before upper pages are needed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The command execution order is made dynamic rather than fixed. The controller adapts the execution sequence based on real-time conditions, such as page interference levels and data dependencies, allowing flexible reordering of commands to optimize performance while maintaining correctness.

Inventive Principle:
Principle #15Dynamics

2Productivity

If upper pages are read before lower pages, then certain performance optimizations are achieved, but interference between pages increases

Engineering Contradiction:
Improveread operation speedVSAvoidpage interference
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The system performs preliminary identification of interference patterns between pages before execution. By analyzing the command sequence in advance, the controller determines which pages should be read first to minimize interference, and executes them in that optimized order rather than following the original sequence.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system converts the potential harm of page interference into a benefit by strategically ordering reads. By recognizing that certain pages cause interference when read together, the controller separates their execution or adjusts timing to exploit the interference pattern in a controlled manner, improving overall performance.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Loss of time

If commands are executed strictly in sequence order, then data consistency is simplified to maintain, but latency increases due to suboptimal execution paths

Engineering Contradiction:
Improvecommand execution latencyVSAvoidexecution order management
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The controller performs preliminary analysis of the command sequence to identify optimal execution paths before execution begins. It determines in advance which commands should be executed first to minimize latency, such as executing lower page reads before upper page reads when interference is detected, and prepares the execution plan accordingly.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where the controller monitors execution conditions and adjusts the command sequence dynamically. Based on observed interference patterns and performance characteristics, the controller refines the execution order to minimize latency while maintaining data consistency.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9250814B2Command order re-sequencing in non-volatile memory
Publication Date: 2016.02.02 APPLE INC
  • US9250814B2 patent drawing
  • US9250814B2 patent drawing
  • US9250814B2 patent drawing

AI summary

An apparatus includes a memory and storage circuitry. The storage circuitry is configured to receive at least one request causing execution of a sequence of memory commands in the memory, to identify that, although a first memory command appears in the sequence before a second memory command, the execution of the second memory command would improve a performance of the execution of the first memory command, and to execute the second memory command and then to execute the first memory command with the improved execution performance.