Memory System Command Resetting and Distribution

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Solution Overview

Problem

Existing memory systems face inefficiencies in managing and rearranging execution sequences of commands from a host, leading to suboptimal data processing speeds due to uncontrolled command execution order and inefficient distribution across memory devices.

Innovation Solution

A memory system that includes a command storage unit and a resetting unit, which classifies and prioritizes commands based on logical and physical addresses, use times, and command lengths to optimize execution sequences and distribute them across multiple memory devices, ensuring efficient data processing by resetting and rearranging command execution orders.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If commands are executed in sequential order from host, then command execution simplicity is maintained, but data processing speed deteriorates due to unoptimized execution sequences

Engineering Contradiction:
Improvedata processing speedVSAvoidcommand management complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-classifying and prioritizing commands before execution. The controller classifies commands into multiple queues based on execution conditions (read/write operations, memory device types, command lengths) and assigns priorities beforehand, so that when commands need to be executed, they are already organized in an optimal sequence, eliminating the need for complex real-time decision-making while maximizing processing speed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the single command stream into multiple classification queues (first queue for read commands, second queue for write commands, etc.). By dividing the command execution flow into separate segments based on operation type and characteristics, the system can process different command types in parallel or in optimized sequences, improving overall data processing speed without creating excessive complexity through manageable queue structures.

Inventive Principle:
Principle #1Segmentation

2Productivity

If commands are distributed to memory devices without rearrangement, then system simplicity is maintained, but productivity deteriorates due to inefficient command distribution

Engineering Contradiction:
Improvesystem efficiencyVSAvoidcommand distribution complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies local quality by assigning different distribution strategies to different types of commands based on their specific characteristics. Read commands are distributed according to read-ahead patterns, write commands are grouped by memory device, and long commands are prioritized differently from short commands. This localized optimization for each command type maximizes system productivity while keeping the overall system manageable through consistent classification rules.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameter of command execution order by dynamically adjusting execution sequences based on command characteristics such as operation type (read/write), command length, and memory device state. The controller modifies execution priorities and distribution patterns according to these parameters, transforming a static sequential execution model into a dynamic optimized execution model that maximizes productivity without requiring complex manual intervention.

Inventive Principle:
Principle #35Parameter changes

3Speed

If command execution sequences are optimized through classification and prioritization, then data processing speed is improved, but device complexity increases due to additional control mechanisms

Engineering Contradiction:
Improvedata processing speedVSAvoidcontrol mechanism complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent reduces control mechanism complexity by performing classification and prioritization actions preliminarily, before the actual execution phase. Commands are sorted into queues and assigned priorities in advance based on their characteristics, so that during execution, the controller simply follows the pre-established queue order without needing complex real-time decision logic. This preliminary organization simplifies the control mechanisms while maintaining high processing speeds.

Inventive Principle:
Principle #10Preliminary action

4Loss of time

If all commands are processed without exclusion, then command completeness is maintained, but processing delays increase due to inefficient handling of long commands

Engineering Contradiction:
Improveprocessing delayVSAvoidcommand handling complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent applies the extraction principle by identifying and separating long commands from the general command stream. Commands exceeding a predetermined length threshold are extracted and placed in a separate prioritized queue, allowing them to be executed independently without blocking or delaying the processing of shorter commands. This extraction of problematic long commands reduces overall processing delays while maintaining complete handling of all commands through a structured multi-queue system.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS9754675B2Memory system and operation method thereof
Publication Date: 2017.09.05 SK HYNIX INC
  • US9754675B2 patent drawing
  • US9754675B2 patent drawing
  • US9754675B2 patent drawing

AI summary

A memory system may include a command storage unit for storing maximum N commands received from a host, K memory devices each for storing maximum M commands based on the maximum N commands and performing each set operation in response to the stored maximum M commands in order of input, and a resetting unit for resetting execution sequences of the maximum N commands based on execution information regarding each of the maximum N commands and the maximum M commands in each of the K memory devices whenever the commands received from the host are stored in the command storage unit, and distributing the N commands to the K memory devices. The execution information includes a logical address, a physical address, a length, and a use time of a corresponding command.