Memory Command Scheduler Circuitry for DRAM Latency Optimization
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Solution Overview
Problem
Existing memory access systems do not optimize memory access commands effectively, leading to suboptimal memory performance due to inefficient scheduling and constraints such as non-uniform access latency and timing characteristics in memory devices like DRAM.
Innovation Solution
An apparatus comprising interface, scheduler, and dispatch circuitry that receives memory access commands, stores and determines the optimal order based on the states and transitions of the memory device, considering constraints and optimization parameters like time and power consumption, to improve memory access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory access commands are issued in the order received from processing circuitry, then the system is simple to implement, but memory performance is suboptimal due to non-uniform access latency and timing constraints
Solution Approach 1:
The patent applies preliminary action by pre-determining the optimal order of memory access commands before they are issued to the memory device. The scheduling system analyzes the sequence of incoming commands and reorders them in advance based on predicted memory access patterns, timing constraints, and latency characteristics. This allows the system to optimize memory performance proactively rather than reactively, achieving better throughput without adding complex real-time decision-making mechanisms during command execution.
2Productivity
If the intermediate device performs scheduling operations to re-order commands, then memory performance improves, but the complexity of the intermediate device increases
Solution Approach 1:
The patent applies dynamics by implementing a flexible scheduling mechanism that can adapt its reordering strategy based on the specific characteristics of incoming memory commands and the current state of the memory device. The scheduling system dynamically adjusts command sequences considering factors such as access latency variations, timing constraints, and memory bank states. This dynamic approach enables the intermediate device to optimize memory performance while maintaining reasonable complexity by only performing reordering operations when beneficial.
3Loss of time
If commands are reordered to optimize access time, then overall memory access time is reduced, but the scheduling process becomes more complex
Solution Approach 1:
The patent applies self-service by designing a scheduling system that autonomously optimizes command ordering without requiring external intervention or complex control mechanisms. The scheduling logic embedded in the intermediate device independently analyzes incoming commands, determines optimal sequencing based on memory timing characteristics, and executes the reordering automatically. This self-service approach reduces overall access time while keeping the scheduling mechanism relatively simple by leveraging the inherent structure of memory access patterns rather than imposing complex external optimization algorithms.
Data Source
AI summary
Examples of the present disclosure relate to an apparatus comprising interface circuitry to receive memory access commands directed to a memory device, each memory access command specifying a memory address to be accessed. The apparatus comprises scheduler circuitry to store a representation of a plurality of states accessible to the memory device and, based on the representation, determine an order for the received memory access commands. The apparatus comprises dispatch circuitry to receive the received memory access commands from the scheduler circuitry and issue the received memory access commands, in the determined order, to be performed by the memory device.