Memory Module Command Training for DRAM Signal Skew

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Solution Overview

Problem

The challenge lies in implementing high-capacity dynamic random access memory (DRAM) within a limited area due to the difficulty in reducing DRAM cell size, which restricts the integration of multiple DRAMs in a memory module.

Innovation Solution

A memory module with a control device that performs command/address training on semiconductor memory devices, adjusting skew between command/address and clock signals through loopback pins, allowing autonomous operation and improved timing margins without external intervention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple DRAMs are provided in the form of a memory module to implement high-capacity, then storage capacity is improved, but device complexity increases

Engineering Contradiction:
Improvestorage capacityVSAvoiddevice complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The memory module is divided into multiple independent DRAM chips, each capable of autonomous operation. The control device is segmented to independently control each DRAM chip, allowing parallel operation and reducing the complexity burden on a single controller.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each DRAM chip is equipped with autonomous training capability, performing command/address training independently without requiring external intervention. This self-service approach reduces the control complexity for the memory module as a whole while enabling high-capacity operation.

Inventive Principle:
Principle #25Self-service

2Measurement precision

If command/address training is performed externally to adjust skew, then timing precision is improved, but operation time is increased

Engineering Contradiction:
Improvetiming precisionVSAvoidoperation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

Command/address training is performed once during initialization to establish optimal skew settings. The trained parameters are then stored and reused during normal operation, eliminating the need for repeated training and reducing time loss while maintaining timing precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The DRAM chip performs autonomous command/address training using its own internal resources and loopback pins, eliminating the need for external controller intervention during training. This self-service approach reduces the time burden on the external system while achieving precise skew adjustment.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10872653B2Memory modules, memory systems, and methods of operating memory modules
Publication Date: 2020.12.22 SAMSUNG ELECTRONICS CO LTD
  • US10872653B2 patent drawing
  • US10872653B2 patent drawing
  • US10872653B2 patent drawing

AI summary

A memory module includes semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. The control device receives a command, an address, and a clock signal from an external device, and provides the command, the address, and the clock signal to the semiconductor memory devices. The control device, in a hidden training mode during a normal operation, performs a command/address training on at least one semiconductor memory device of the semiconductor memory devices by transmitting a first command/address and a first clock signal to the at least one semiconductor memory device and receiving a second command/address and a second clock signal in response to the first command/address and the first clock signal, from the at least one semiconductor memory device.