Nonvolatile Memory Command Suspension via Chip State Backup
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently managing command execution, particularly in suspending and resuming operations without data loss or errors, especially in high-speed and integrated 3D memory systems like vertical NAND flash memory devices.
Innovation Solution
A nonvolatile memory device with a memory cell array, row decoder, page buffer, and control logic that allows for safe suspension and resumption of command execution by backing up and restoring chip information using external or internal storage spaces, ensuring data integrity during operations like erase commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If command execution is suspended during erase or program operations, then operational flexibility is improved, but data integrity and reliability deteriorate due to potential data loss or errors
Solution Approach 1:
The patent applies preliminary action by backing up chip information to external storage before suspending command execution. The control logic stores critical chip state information in advance, so when suspension occurs, the data integrity is preserved and the operation can be accurately resumed later without data loss or errors.
2Speed
If chip information is stored in internal control logic during command execution, then access speed is improved, but reliability deteriorates due to potential data loss during suspension
Solution Approach 1:
The patent extracts critical chip information from the internal control logic and stores it in external storage space. This separation allows the control logic to maintain fast access for active operations while the external storage provides a safe backup that prevents data loss during command suspension, resolving the conflict between speed and reliability.
3Productivity
If command execution is resumed without restoring chip information, then operational speed is improved, but reliability deteriorates due to incorrect chip conditions
Solution Approach 1:
The patent implements feedback by retrieving the backed-up chip information from external storage before resuming command execution and using this information to restore the chip to its correct previous state. This feedback mechanism ensures that the chip conditions are accurately restored, maintaining reliability while allowing fast resumption of operations.
Data Source
AI summary
A nonvolatile memory device includes a memory cell array, a row decoder, a page buffer, and control logic. The memory cell array includes memory cells connected to word lines and bit lines, the memory cell array being configured to store data. The row decoder is configured to selectively activate a string selection line, a ground selection line, and the word lines of the memory cell array. The page buffer is configured to temporarily store external data and to apply a predetermined voltage to the bit lines according to the stored data during a program operation, and to sense data stored in selected memory cells using the bit lines during a read operation or a verification operation. The control logic is configured to control the row decoder and the page buffer. During execution of commands, when a request to suspend the execution of the commands is retrieved, chip information is backed up to a storage space separate from the control logic.