Semiconductor Memory Command Timing Collision Resolution

The patent applies preliminary action by detecting command input timing in advance and proactively adjusting subsequent command timing. The detection unit identifies when commands are inputted earlier than the minimum operation interval, and the shifting unit pre-adjusts the timing of internal operations to compensate for this early input, ensuring that internal operations maintain proper timing accuracy despite accelerated command input speed.

The patent implements feedback by using the detection unit to continuously monitor command input timing and provide information to the shifting unit. When commands are inputted at intervals shorter than the minimum operation interval (such as 2tCK between active commands), the detection unit detects this condition and feeds back to the shifting unit, which then adjusts the timing of internal operations accordingly. This closed-loop feedback mechanism maintains command timing accuracy and prevents timing collisions even when productivity is improved through reduced command intervals.

The patent applies segmentation by dividing the command processing function into separate units: the detection unit that monitors command input timing, the latching unit that captures command signals, and the shifting unit that adjusts timing. When multiple commands are inputted simultaneously or at intervals shorter than the minimum operation interval, this segmented architecture allows each unit to handle its specific task independently, preventing command collisions and ensuring that internal operations are performed at the correct timing without delay.