3D Memory Device With Common Control Electrode Switches
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Solution Overview
Problem
Current semiconductor technology faces challenges in shrinking device size while maintaining efficiency, density, and reducing costs, particularly in the development of memory devices where feature sizes and operation speed are critical.
Innovation Solution
A memory device and manufacturing method involving a stacked structure with a pillar structure and electrode layers, where memory cells are defined at intersections between channel lines and word lines, with switches connected to manage electrical connections and operations, allowing for efficient programming, reading, and erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If feature sizes are shrunk to reduce device size, then device density is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent transitions from planar 2D memory architecture to 3D vertical architecture by stacking multiple memory cell layers vertically. This dimensional change allows continued scaling of storage capacity without further reducing lateral feature sizes, thereby maintaining manufacturability while increasing device density.
Solution Approach 2:
The memory device is divided into multiple discrete memory cell layers stacked vertically, with each layer containing memory cells formed at intersections of channel lines and word lines. This segmentation allows independent formation and optimization of each layer, maintaining manufacturing precision while achieving high density through vertical stacking.
2Productivity
If device size is reduced, then integration density is improved, but operation speed tends to decrease
Solution Approach 1:
By moving to 3D vertical stacking, the patent achieves higher integration density without increasing lateral dimensions that would increase signal transmission distances. The vertical architecture maintains shorter current paths and faster operation speeds while packing more memory cells into the same footprint area.
Solution Approach 2:
The patent implements dynamic voltage control through select gates and control electrodes that can independently regulate voltage levels for different memory cell layers. This dynamic control optimizes read/write operation speeds by applying appropriate voltages to activate specific layers, maintaining fast operation despite increased density.
3Productivity
If device size is reduced, then cost per integrated circuit is reduced, but maintaining electrical performance becomes more difficult
Solution Approach 1:
The vertical 3D architecture achieves higher capacity in the same footprint, reducing cost per integrated circuit. The stacked layer structure with shared channel lines and independently controlled word lines maintains electrical performance by providing multiple parallel access paths and robust signal routing.
Solution Approach 2:
The control electrodes and select gates serve multiple functions: they act as control gates for memory cell access, voltage regulators for different layers, and selection switches for read/write operations. This multi-functionality maintains electrical performance while reducing the number of separate components needed, lowering manufacturing cost.
Data Source
AI summary
A memory device and a manufacturing for the same are provided. The memory device comprises a channel line, word lines, a first switch, and a second switch. Memory cells for a memory string are defined at intersections between the channel line and the word lines. The first switch is electrically connected with the channel line. The second switch is electrically connected with the channel line. The first switch is electrically connected between the second switch and the memory cells.