Memory Compaction Management for SLC-to-QLC Data Integrity
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Solution Overview
Problem
Memory devices face performance penalties due to significant latency and data bus congestion caused by the need to read, error check, and reprogram SLC data multiple times during coarse-fine programming operations for QLC memory, particularly in NAND flash devices.
Innovation Solution
Implement memory compaction management by a memory sub-system controller that performs corrective or internal copyback operations, optimizing data integrity and validity checks before programming SLC data into QLC memory, reducing the need for repeated data transfers and error corrections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SLC data is read, error checked, and reprogrammed multiple times during coarse-fine programming operations for QLC memory, then data integrity is ensured, but latency increases and data bus congestion occurs
Solution Approach 1:
The patent performs error checking on SLC data before the copyback operation (pre-programming validation). By validating data integrity in advance and only copying back error-free data, the system avoids multiple reprogramming cycles, thereby reducing latency while ensuring data integrity.
2Reliability
If SLC data is transferred multiple times during coarse-fine programming operations, then data validity is verified, but data bus congestion increases
Solution Approach 1:
The patent performs validation of SLC data before initiating the copyback operation. By pre-checking data validity and filtering out erroneous data beforehand, the system minimizes the number of data transfers required, thereby reducing data bus congestion while maintaining data validity.
3Manufacturing precision
If multiple copyback operations are performed for SLC to QLC programming, then programming accuracy is improved, but overall programming speed decreases
Solution Approach 1:
The patent performs pre-programming validation by error-checking SLC data before the copyback operation. This preliminary check ensures that only valid data is copied back, improving programming accuracy while reducing the need for iterative corrections, thereby maintaining faster programming speeds.
4Reliability
If error checking is performed on SLC data before copyback, then data quality is improved, but processing time increases
Solution Approach 1:
The patent performs error checking on SLC data as a preliminary step before the copyback operation. While this adds initial processing time, it prevents multiple subsequent reprogramming cycles by ensuring data quality upfront, thereby reducing total processing time and improving overall efficiency.
Data Source
AI summary
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a first set of memory cells to obtain a data integrity metric value; responsive to determining that the data integrity metric value satisfies a threshold criterion, determining whether a threshold number of second sets of memory cells, configured to store the first number of bits per memory cell, are available for a memory management operation; and responsive to determining that the threshold number of second sets of memory cells are available, causing the memory device to perform the memory management operation by copying data from the first set of memory cells and from the threshold number of second sets of memory cells to a third set of memory cells.