Compensation Circuit for Memory Sense Amplifier Offset

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Solution Overview

Problem

In memory devices, the offset in sense amplifiers due to process variations and temperature affects the effective sensing margin, leading to increased time required for activating a word line and unnecessary power consumption during compensation operations.

Innovation Solution

A compensation circuit and method that simultaneously start the fuse compare and compensation operations in response to an active command, stopping the compensation operation for unselected word lines once the fuse compare is completed, thereby reducing the time required for activating a word line and minimizing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If compensation operation is performed for all sense amplifiers before fuse compare is completed, then effective sensing margin is ensured, but power consumption increases and operation time increases

Engineering Contradiction:
Improveeffective sensing marginVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies local quality by differentiating the compensation operation treatment between selected and unselected word lines. After fuse compare completion, compensation is stopped for unselected word lines while continuing for selected word lines. This localized approach ensures sensing margin is maintained where needed while reducing unnecessary power consumption in areas where compensation is no longer required.

Inventive Principle:
Principle #3Local quality

2Reliability

If compensation operation is performed for all sense amplifiers before fuse compare is completed, then effective sensing margin is ensured, but operation time increases

Engineering Contradiction:
Improveeffective sensing marginVSAvoidoperation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent employs preliminary action by starting the compensation operation simultaneously with the fuse compare operation in response to an active command. This allows the compensation to begin in advance for selected word lines, ensuring the sensing margin is ready before the fuse compare completes, while avoiding extended operation time by stopping compensation for unselected word lines once the compare is done.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If fuse compare and compensation operation are performed sequentially, then operation control is simple, but time required for activating word line increases

Engineering Contradiction:
Improveoperation controlVSAvoidtime for activating word line
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent merges the fuse compare operation and compensation operation into parallel simultaneous operations. Both operations are initiated together in response to an active command, and the compensation operation is coordinated to stop for unselected word lines upon fuse compare completion. This merging reduces the total time for word line activation while the control circuit manages the coordination to maintain operational control.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9455051B1Compensation circuit and compensation method
Publication Date: 2016.09.27 MIMIRIP LLC
  • US9455051B1 patent drawing
  • US9455051B1 patent drawing
  • US9455051B1 patent drawing

AI summary

Provided is a compensation circuit including a memory cell array including a normal area and a redundancy area for repairing defects occurred in the normal area, a compensation time control circuit that activates a compensation start signal for a sense amplifier coupled to the normal area and the redundancy area in response to an active command, and a compensation control signal generation circuit that starts a compensation operation in response to the compensation start signal, and stops a compensation start signal for a sense amplifier coupled to an unselected word line in response to a fuse compare completion pulse and a compare address.