Memory Compiler Layout Integration with Standard Cell Rows
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Solution Overview
Problem
The inefficiencies in integrated circuit layout design due to the inclusion of on-chip memory devices result in wasted space, particularly at the boundary between memory instances and standard cells, leading to increased area requirements and manufacturing costs, especially as memory instances become smaller and process geometries shrink.
Innovation Solution
A method is introduced where a memory compiler operates in an integration enhancement mode, referencing properties of the standard cell library to generate memory instances that minimize area overhead at the boundary with standard cells, such as by constraining the memory instance's width to be an integer multiple of the standard cell row height and reducing the number of polysilicon interface regions, thereby eliminating unnecessary space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a memory compiler generates memory instances without referencing standard cell library properties, then the memory instance can be generated independently and quickly, but area overhead at the boundary between memory instance and standard cells increases
Solution Approach 1:
The memory compiler performs preliminary actions by referencing standard cell library properties during memory instance generation. Specifically, it aligns the memory instance width to be an integer multiple of the standard cell row height and positions polysilicon interface regions accordingly, so that when the place and route tool integrates them, no wasted space occurs at the boundary.
2Adaptability or versatility
If the memory instance width is not aligned to standard cell row height, then the memory instance can accommodate various memory sizes flexibly, but wasted space occurs at the boundary where standard cells cannot be placed
Solution Approach 1:
The memory compiler changes the width parameter of the memory instance to be an integer multiple of the standard cell row height. This parameter adjustment ensures that the memory instance width aligns with the standard cell grid, eliminating wasted space at the boundaries while still accommodating various memory sizes through the compiler's size specification capabilities.
3Reliability
If polysilicon interface regions are provided between memory instance and standard cells, then separation and isolation are achieved, but the area required increases
Solution Approach 1:
The invention merges the polysilicon interface regions with the standard cell rows by aligning them to the same horizontal positions. The memory instance is positioned such that its boundaries coincide with polysilicon interface region boundaries, allowing standard cells to be placed directly adjacent to the memory instance without additional separation space, thus eliminating wasted area while maintaining proper isolation.
Data Source
AI summary
A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler.