Memory Compiler Scaling for PVT Corner Characterization
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Solution Overview
Problem
The existing methods for characterizing and generating memory instances in semiconductor chip designs are time-consuming and inefficient, especially when dealing with various configurations and PVT corners, leading to a need for improved memory compiler techniques.
Innovation Solution
The implementation of a memory compiler architecture that uses intelligent scaling and interpolation methods to derive optimized sets of memory instances, reducing the need for extensive characterization and simulation across multiple PVT corners, thereby improving efficiency and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional memory instance characterization methods are used across multiple PVT corners, then comprehensive timing and power data is obtained, but the process becomes extremely time-consuming and inefficient
Solution Approach 1:
The patent performs preliminary characterization at a reference PVT corner to establish baseline timing and power data. This preliminary action allows subsequent corners to be derived through scaling rather than full re-characterization, significantly reducing total characterization time while maintaining accuracy.
Solution Approach 2:
The patent changes the approach from characterizing each PVT corner independently to using parameter scaling based on pre-characterized reference data. By establishing relationships between PVT parameters at the reference corner, the system can efficiently derive characteristics at other corners through parameter transformation rather than exhaustive simulation.
2Reliability
If full characterization is performed for all memory instance configurations, then complete design coverage is achieved, but the complexity and resource requirements increase substantially
Solution Approach 1:
The patent creates a universal characterization framework where a single reference corner characterization serves multiple purposes. The same reference data and scaling relationships are used to derive characteristics across all PVT corners and memory configurations, eliminating the need for separate characterization processes for each case.
Solution Approach 2:
The patent copies the characterization methodology from the reference corner to other corners through systematic scaling. Instead of performing independent characterization for each corner, the system creates scaled versions of the reference characterization, significantly reducing process complexity while maintaining design coverage.
3Measurement precision
If extensive simulation is performed for all PVT corners, then accurate timing arcs are obtained, but the productivity and time-to-market are reduced
Solution Approach 1:
The patent performs preliminary timing arc extraction at the reference corner to establish accurate baseline data. This preliminary timing characterization enables subsequent corners to be derived through scaling relationships, maintaining timing arc accuracy while dramatically reducing the total simulation time required across all PVT corners.
Data Source
AI summary
Various implementations described herein are directed to a system and methods for memory compiling. For instance, a method may include selecting source corners from a memory compiler configuration and generating a standardized set of memory instances for the selected source corners. Also, the method may include deriving a reduced set of memory instances based on the standardized set of memory instances and building a memory compiler database for a compiler space based on the standardized set of memory instances and the reduced set of memory instances.