Memory Compiler Optimizing Speed Power Area
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory compilers are inefficient in generating optimized memory instances as they typically consider only one factor (speed, power, or area) and operate at a device level, making it time-consuming to meet client requirements.
Innovation Solution
A memory compiler that operates at architecture, block, and device levels, using a top-down and bottom-up approach to optimize memory design among speed, power, and area by decomposing memory into building blocks, modifying device parameters, and assembling them to generate optimized instances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional memory compilers consider only one factor (speed, power, or area) to generate memory instances, then the generation process is simple, but the generated memory instances are not optimized to client requirements
Solution Approach 1:
The memory compiler is segmented into multiple independent modules: architecture-level compiler, block-level compiler, and device-level compiler. Each module handles specific aspects of memory optimization independently, allowing the system to consider multiple factors (speed, power, area) simultaneously while maintaining manageable complexity through modular architecture.
Solution Approach 2:
The memory compiler is designed as a universal system that can optimize for multiple factors (speed, power, and area) simultaneously. The multi-level compiler structure enables the system to perform diverse optimization functions at different abstraction levels, making it adaptable to various client requirements without requiring separate specialized compilers for each optimization goal.
2Manufacturing precision
If conventional memory compilers operate at device-level manner to optimize memory instances, then detailed optimization can be achieved, but it is very time-consuming
Solution Approach 1:
The architecture-level and block-level compilers perform preliminary optimization actions at higher abstraction levels before detailed device-level optimization. By pre-determining optimal memory configurations and block structures at architecture and block levels, the device-level compiler receives pre-processed data that requires less detailed optimization, significantly reducing the time-consuming nature of device-level optimization while maintaining precision.
Solution Approach 2:
The invention introduces a multi-level abstraction dimension to the optimization process. Instead of operating solely at the device level, the system adds architecture-level and block-level dimensions, allowing optimization to proceed from high-level conceptual designs down to detailed device implementations. This dimensional approach enables parallel processing at different levels and reduces the computational burden at any single level.
3Productivity
If memory is decomposed into building blocks and parameters are modified through top-down and bottom-up approaches, then optimized memory instances can be generated rapidly, but the optimization process becomes more complex
Solution Approach 1:
The memory design is segmented into standard building blocks (memory cells, word lines, bit lines, decoders, etc.) that can be independently optimized and recombined. The top-down approach decomposes memory into these blocks, while the bottom-up approach reconstructs memory from optimized blocks. This segmentation enables rapid generation of optimized instances through modular assembly while managing complexity through standardized block interfaces.
Solution Approach 2:
The optimization process dynamically switches between top-down decomposition and bottom-up reconstruction based on design requirements. The system can adaptively apply different optimization strategies at different stages: top-down for initial architecture planning and bottom-up for detailed implementation. This dynamic approach accelerates generation speed by selecting the most efficient optimization path while managing process complexity through conditional execution.
Data Source
AI summary
A method of generating optimized memory instances using a memory compiler is disclosed. Data pertinent to describing a memory to be designed are provided, and front-end models and back-end models are made to supply a library. Design criteria are received via a user interface. Design of the memory is optimized among speed, power and area according to the provided library and the received design criteria, thereby generating memory instances.