Memory System Compresses Address Mapping for Faster Read Access

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Solution Overview

Problem

Current memory systems experience performance degradation due to the large amount of logical-to-physical address mapping information that needs to be loaded from nonvolatile memory devices, which hinders read operations and requires efficient management to enhance performance.

Innovation Solution

A memory system that compresses logical-to-physical address mapping information, stores the compressed data in a buffer memory, and manages compression classes to optimize storage and retrieval, allowing for efficient read and write operations by allocating memory space based on compression classes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If logical-to-physical address mapping information is stored in buffer memory without compression, then address mapping can be performed, but the buffer memory occupies large capacity and read performance is degraded

Engineering Contradiction:
Improveread performanceVSAvoidbuffer memory capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent applies asymmetry by implementing different storage strategies for different types of address mapping information. Frequently accessed and highly compressible mapping entries are stored in compressed form in the buffer memory, while less frequently accessed or less compressible entries are stored in uncompressed form in the nonvolatile memory device. This asymmetric approach optimizes buffer memory utilization by storing only the most beneficial entries in compressed format, thereby improving read performance for hot data while minimizing the buffer memory capacity required.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent employs parameter changes by dynamically adjusting the compression level and format of address mapping information based on access patterns and buffer memory availability. The system monitors the usage frequency of address mappings and adjusts the compression ratio accordingly - highly frequent mappings use higher compression ratios, while less frequent mappings use lower compression ratios or remain uncompressed. This dynamic parameter adjustment allows the system to optimize between read performance and buffer memory capacity utilization.

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If compressed address mapping information is stored in buffer memory, then buffer memory capacity is reduced, but additional compression and decompression operations are required

Engineering Contradiction:
Improvebuffer memory capacityVSAvoidcompression management complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-compressing address mapping information during the address translation process before it is stored in the buffer memory. The compression is performed as part of the normal address mapping operation, so that when data is read from the buffer memory, it is already in the optimized compressed format. This eliminates the need for separate compression steps and reduces the overall complexity of the system by integrating compression into the existing address translation pipeline.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements self-service through automatic compression class classification and management. The memory controller automatically determines the compression class of each address mapping entry based on its characteristics and access pattern, selecting the appropriate compression ratio without requiring external intervention. The system also automatically manages the buffer memory contents, evicting less frequently accessed compressed entries and loading new entries with appropriate compression levels, thereby reducing the operational complexity for users.

Inventive Principle:
Principle #25Self-service

3Productivity

If compression classes are managed for address mapping information, then storage efficiency is improved, but memory management complexity increases

Engineering Contradiction:
Improvestorage efficiencyVSAvoidcompression class management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies partial action by implementing compression class management only for the most frequently accessed address mapping entries that benefit most from compression. Rather than applying complex multi-level compression management to all address mappings in the system, the patent selectively applies compression class management to a subset of entries that are identified as having high access frequency and high compressibility. This partial approach achieves significant storage efficiency improvements while avoiding the full complexity of comprehensive compression management.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10831652B2Memory system and operating method thereof
Publication Date: 2020.11.10 SK HYNIX INC
  • US10831652B2 patent drawing
  • US10831652B2 patent drawing
  • US10831652B2 patent drawing

AI summary

In a memory system and an operating method thereof, the method includes: receiving a read command and a read logical address; reading a raw map slice stored in a nonvolatile memory device, in a map read phase, in response to the read command, wherein the raw map slice includes a read physical address corresponding to the read logical address; generating a compressed map slice by compressing the raw map slice; storing a compression class corresponding to a ratio of a size of the compressed map slice to a size of the raw map slice in a compression class description table; storing the compressed map slice in a buffer memory; and reading data corresponding to the read command from the nonvolatile memory device, in a data read phase, based on the compressed map slice stored in the buffer memory.