Memory Device Compress and Read-Write-Back Testing
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Solution Overview
Problem
Conventional memory device testing methods using external stress equipment are inefficient and costly, often failing to detect all elements within the reading and writing circuits, leading to reduced product yield due to undetected errors.
Innovation Solution
A memory device with a compress test mode and read with write back test mode that writes and reads test data multiple times through different paths to ensure comprehensive error detection, utilizing a test circuit to compare original and read data for error determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external stress equipment is used to test all elements and storage blocks corresponding to each electronic PAD, then testing completeness is improved, but testing cost and complexity increase significantly
Solution Approach 1:
The patent segments the testing process into two distinct modes: compress test mode for rapid initial screening and read with write back test mode for comprehensive verification. This segmentation allows different testing strategies to be applied to different subsets of elements, reducing overall testing complexity while maintaining completeness.
Solution Approach 2:
The compress test mode serves as a preliminary action that quickly identifies obviously defective devices before committing resources to more comprehensive read with write back testing. This preliminary screening reduces the number of devices that require expensive and time-consuming complete testing.
2Device complexity
If a single electronic PAD is used to obtain test results for various reading and writing circuits and storage blocks, then testing cost is reduced, but some elements may not be detected leading to undetected errors
Solution Approach 1:
The patent makes the single electronic PAD universal by implementing two different test modes that can collectively test all elements. The compress test mode tests certain elements while the read with write back test mode tests other elements, and together they provide complete coverage of all reading and writing circuits and storage blocks.
Solution Approach 2:
The patent changes the operational parameters of the test circuit between two modes: compress test mode with specific compression ratios and read with write back test mode with different operational characteristics. This parameter change allows the same hardware to perform different testing functions that collectively cover all elements.
3Productivity
If conventional compress test mode is used, then testing efficiency is improved, but testing precision is insufficient as not all elements can be detected
Solution Approach 1:
The patent implements a dynamic testing strategy that adapts between two modes based on testing needs. The compress test mode provides high-speed initial screening, while the read with write back test mode provides thorough verification when needed, creating a dynamic system that optimizes both efficiency and precision.
Solution Approach 2:
The testing process employs periodic action by alternating between compress test operations and read with write back test operations. This periodic switching allows the system to maintain high efficiency through frequent compress testing while periodically performing comprehensive read with write back testing to ensure precision.
Data Source
AI summary
A method for testing a memory device is disclosed. The method includes: respectively writing at least one test data into a plurality of storage blocks in the memory device such that a plurality of first time written test data are stored in the storage blocks; in a read with write back test mode, reading the first time written test data from the storage blocks in the memory device and writing the plurality of first time written test data into the storage blocks to generate a plurality of second time written test data; and in a compress test mode, reading the plurality of second time written test data from the storage blocks by a compress test operation and determining whether the memory device operates erroneously according to the plurality of second time written test data and the test data.