Memory Compression for Non-Contiguous Read/Write Address Mapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory compression techniques are limited by their requirement for sequential writing to contiguous memory locations, which restricts their ability to accommodate non-sequential compression and introduce delays due to the need for a temporary buffer to accumulate data samples before writing.
Innovation Solution
A system and method that allow for the compression of data quantities read from a first memory along a specific orientation and writing them to a second memory along a different orientation, enabling non-sequential storage and eliminating the need for a temporary buffer by directly transferring compressed data quantities to non-sequential addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is compressed using a temporary buffer to accumulate samples before writing, then compression efficiency is improved, but access time and device complexity increase due to buffering delays
Solution Approach 1:
The patent extracts the temporary buffer component from the compression system entirely. Instead of accumulating samples in a buffer before compression, the system performs compression on incoming data samples directly as they arrive, eliminating the buffering delay and reducing access time while maintaining compression efficiency.
Solution Approach 2:
The patent applies preliminary compression action by compressing data samples immediately upon receipt rather than waiting to accumulate a full buffer. This preliminary compression of individual samples or small groups eliminates the need for buffer accumulation delays, resolving the contradiction between compression efficiency and access time.
2Device complexity
If compression writes to sequential memory addresses, then device complexity is reduced, but adaptability is limited for non-sequential compression requirements
Solution Approach 1:
The patent implements dynamic address selection for memory writes, allowing the system to adaptively choose between sequential and non-sequential write patterns based on application requirements. This dynamic addressing capability increases adaptability for various compression scenarios while the underlying compression engine remains relatively simple, balancing device complexity and versatility.
Solution Approach 2:
The patent creates a universal compression interface that can write to both sequential and non-sequential memory addresses through a unified compression engine. This multi-functional capability allows the same compression hardware to serve diverse applications with different memory access patterns, enhancing adaptability without proportionally increasing device complexity.
3Manufacturing precision
If a temporary buffer is used to store data samples before compression, then compression quality is improved, but device complexity and memory requirements increase
Solution Approach 1:
The patent removes the temporary buffer from the compression architecture, achieving compression quality through direct processing of incoming samples. By eliminating the buffer component entirely, the system reduces device complexity and memory requirements while maintaining acceptable compression quality through immediate compression of data as it arrives.
Solution Approach 2:
The compression system performs self-service by processing and compressing data samples immediately upon receipt without requiring external buffer storage. This self-service approach eliminates buffer management complexity while maintaining compression quality through real-time processing, resolving the contradiction between compression quality and device complexity.
Data Source
AI summary
Disclosed embodiments include a system having a first memory, a second memory, circuitry that reads data quantities from the first memory along a first orientation, a compression engine that compresses each of the read data quantities to produce corresponding compressed data quantities, and circuitry that writes the compressed data quantities to the second memory along a second orientation which differs from the first orientation. The read data quantities have a first bit width and the compressed data quantities have a second bit width that is less than the first bit width.