Semiconductor Memory Compression Unit Parallel Bank Testing
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Solution Overview
Problem
Current semiconductor memory device test technologies are inefficient in reducing test time and screening ability, especially with the increasing complexity of memory cells and the adoption of grouped bank structures, which hinders cost-effective product fabrication.
Innovation Solution
A semiconductor memory device with a compression unit to compress data from multiple memory cells, a latching unit to detect failures, and an output unit to report results, allowing for simultaneous selection and testing of multiple bank groups during a parallel test mode, thereby reducing test time and improving screening efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a plurality of tests are performed to secure reliability of the semiconductor memory device, then the reliability is improved, but the test time increases
Solution Approach 1:
The patent combines multiple test operations into a single parallel test process. By writing the same data to multiple memory cells simultaneously and reading them back in parallel, the system achieves comprehensive reliability testing without proportionally increasing test time. The compression unit merges test results from multiple bank groups into a single comprehensive result.
Solution Approach 2:
The patent segments the memory device into multiple bank groups with separate global input/output lines, allowing independent parallel testing of each segment. This segmentation enables simultaneous testing of multiple memory regions without interference, thereby maintaining reliability while reducing overall test time.
2Loss of time
If a parallel test is performed to reduce test time for a plurality of memory cells, then the test time is reduced, but the screening ability deteriorates
Solution Approach 1:
The patent introduces a compression unit as an intermediary that processes test results from multiple bank groups. This compression unit performs logical operations (such as NOR operations) on the test data to compress multiple results into a single comprehensive result, thereby maintaining screening ability while enabling parallel testing.
Solution Approach 2:
The patent implements a feedback mechanism where the compression unit continuously monitors test results from parallel operations and provides compressed feedback signals. This allows the system to maintain high screening ability by detecting failures in any bank group while operating in parallel test mode.
3Speed
If separate global input/output lines are provided for each bank group to improve performance, then the device performance is improved, but the device complexity increases
Solution Approach 1:
The patent designs the compression unit and latching unit to serve multiple functions: they handle test data compression, result latching, and failure detection across all bank groups. This multi-functionality reduces the need for separate dedicated circuits for each bank group, thereby managing device complexity while maintaining performance benefits.
4Ease of operation
If the same data are written into the plurality of memory cells and XOR logics are used to read the data, then the parallel test operation is simplified, but the screening ability deteriorates
Solution Approach 1:
The patent changes the logical operation parameter from XOR to NOR (or other appropriate logic operations) in the compression unit. This parameter change improves screening ability because NOR operations can detect failures more effectively than XOR operations, while still maintaining the simplicity of the parallel test operation structure.
Data Source
AI summary
A semiconductor memory device includes a compression unit configured to compress a plurality of data, which are read from a memory cell region based on successive read commands and addresses, and to successively output the compressed data during a first test mode, a latching unit configured to latch the compressed data in response to a read strobe signal and to fix the latched value when a fail is detected from the compressed data during the first test mode, and an output unit configured to output the latched value to the outside during a second test mode.