Memory Compression Circuit for Multi-Access Error Detection

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Solution Overview

Problem

Traditional data compression methods are ineffective in memory testing architectures where each individual bit of data corresponds to a different repair address, leading to inefficiencies and increased test time, as they fail to identify the correct repair address for defective bits.

Innovation Solution

A data compression system that compresses bits from multiple memory accesses with distinct repair addresses using comparison logic within a compression block, where each data compression circuit compares bits from different memory accesses to identify errors and generate error data indicating defective memory cells, allowing for efficient identification of defective bits across different repair addresses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If traditional compression methods are used to compress individual bits from a single memory access, then the test time is reduced and the number of output pins is reduced, but the method becomes ineffective when individual bits correspond to different repair addresses, leading to inability to identify correct repair addresses

Engineering Contradiction:

Improvetest timeVSAvoidrepair address identification

Core Design Contradiction:

Loss of timeVSLoss of information

Solution Approach 1:

The patent segments the compression process by organizing memory bits into groups based on their repair addresses. Each group of bits sharing the same repair address is compressed together, while maintaining the association with that repair address. This segmentation allows compression to be applied effectively without losing repair address information, as each compressed group can still be traced back to its corresponding repair address.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary mechanism (the compression circuit with repair address tracking) that sits between the memory array and the output. This intermediary compresses the data while preserving the repair address information through associated logic that tracks which repair address corresponds to which compressed data group, thereby maintaining the ability to identify defective bits even after compression.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Loss of information

If no compression is used during memory testing, then repair address identification is maintained, but test time increases substantially

Engineering Contradiction:

Improverepair address identificationVSAvoidtest time

Core Design Contradiction:

Loss of informationVSLoss of time

Solution Approach 1:

The patent implements a dynamic compression approach where the compression ratio and grouping strategy can adapt based on the memory architecture and repair address distribution. The system dynamically organizes bits into compression groups based on their repair address associations, allowing optimal compression while maintaining repair address traceability throughout the testing process.

Inventive Principle:

Principle #15Dynamics

3Productivity

If data from multiple memory accesses with different repair addresses is compressed together, then compression efficiency is improved, but traditional methods fail to identify which repair address corresponds to defective bits

Engineering Contradiction:

Improvecompression efficiencyVSAvoidrepair address association

Core Design Contradiction:

ProductivityVSLoss of information

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements feedback mechanisms where the compression circuit receives information about repair addresses and uses this feedback to properly associate compressed data with the correct repair addresses. The system continuously monitors and tracks the relationship between compressed data groups and their corresponding repair addresses, ensuring that defective bits can be correctly identified even after compression.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS9183952B2Apparatuses and methods for compressing data received over multiple memory accesses

Publication Date: 2015.11.10 MICRON TECHNOLOGY INC

AI summary

Apparatuses and methods for compressing data responsive to a plurality of memory accesses is described. An example compression circuit includes a comparator configured to compare data provided by a group of memory cells associated with a repair address. Each subset of one or more bits of the data is sequentially provided by the group of memory cells responsive to a respective memory access of a plurality of memory accesses. The example compression circuit further including an error bit latch coupled to the comparison circuit. The error bit latch configured to, responsive to an output received from the comparison circuit indicating an error, compress the data to an error bit by setting the error bit to an error detected state and latching the error bit having the error detected state.