Memory System Data Compression for Column Repair
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory arrays grow in size and density, the amount of data generated during testing for electrical defects increases, leading to longer read-out times and potential memory overflows in testers, necessitating a reduction in the memory used during testing procedures.
Innovation Solution
A memory system that compresses data from multiple column planes into a single bit, allowing for efficient storage and communication of error data, reducing the memory requirements and read-out time by storing only the most recent test results in a register.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory arrays grow in size and density, then storage capacity is improved, but read-out time increases and memory overflow risk in testers worsens
Solution Approach 1:
The patent extracts only the essential error information (single bit indicating presence of errors) from the complete test data, separating the critical defect detection function from the voluminous raw test data. This allows rapid read-out of error status without transmitting or storing complete test datasets, resolving the contradiction between array size and read-out time.
Solution Approach 2:
Instead of storing and reading out complete test data to identify errors, the patent inverts the approach by directly generating and storing only the error indication bits that result from test data analysis. This inversion transforms the data flow from 'store all data then analyze' to 'analyze then store only results', eliminating the read-out time bottleneck.
2Quantity of substance
If memory arrays grow in size and density, then storage capacity is improved, but memory overflow risk in testers worsens
Solution Approach 1:
The patent extracts only the essential error information (single bit indicating presence of errors) from the complete test data, separating the critical defect detection function from the voluminous raw test data. This allows rapid read-out of error status without transmitting or storing complete test datasets, resolving the contradiction between array size and read-out time.
Solution Approach 2:
The patent creates a compressed representation (copy) of the error status that requires minimal storage space. Instead of storing actual test data in tester memory, it stores a simplified copy consisting of single-bit error indicators, dramatically reducing memory requirements and eliminating overflow risk while preserving all necessary defect information.
3Measurement precision
If complete test data is stored and read out, then measurement precision is improved, but read-out time and memory usage increase
Solution Approach 1:
The patent extracts only the essential error information (single bit indicating presence of errors) from the complete test data, separating the critical defect detection function from the voluminous raw test data. This allows rapid read-out of error status without transmitting or storing complete test datasets, resolving the contradiction between array size and read-out time.
Solution Approach 2:
The patent introduces an intermediary processing step that analyzes complete test data internally and converts it into compact error indication bits. This intermediary layer preserves measurement precision by accurately detecting all errors while transforming the data into a compressed format that enables rapid read-out and minimal memory usage.
Data Source
AI summary
Methods, systems, and devices for data compression for global column repair are described. In some cases, a testing device may perform a first internal read operation to identify errors associated with on one or more column planes. A value (e.g., a bit) indicating whether an error occurred when testing each column plane may be stored. The testing device may perform a second internal read operation on the same column planes, or on column planes of a different bank of memory cells. The values (e.g., bits) indicating whether errors occurred during the first internal read operation and the values indicating whether errors occurred during the second internal read operation may be combined and stored in a register. The stored values may be read out (e.g., as a burst) to repair the defective column planes.