Memory Compression for Non-Contiguous Read and Write Addresses
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory compression techniques are limited by their requirement for sequential writing to contiguous memory addresses, which restricts their ability to accommodate non-sequential compression and introduce delays due to the need for a temporary buffer to accumulate data samples before writing.
Innovation Solution
A digital data storage and retrieval system that includes circuitry for reading and writing compressed data quantities to non-sequential addresses in both the source and destination memories, using equations to determine the correct storage locations and enable efficient compression and decompression without a history buffer, allowing for flexible addressing and immediate writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a temporary buffer is used to accumulate data samples before writing to memory, then compression can be achieved, but writing must be sequential to contiguous addresses and delays occur due to buffer accumulation requirements
Solution Approach 1:
The patent extracts the sequential writing constraint from the compression process by calculating target addresses directly using equations that incorporate the original address, compression ratio, and destination memory parameters. This allows compressed data to be written to non-sequential addresses immediately without requiring a temporary buffer to accumulate samples first.
Solution Approach 2:
The patent performs preliminary address calculation using the equations provided, determining the exact destination address for each compressed data element before the compression operation completes. This preliminary address determination eliminates the need for sequential writing and buffer accumulation, as the target locations are predetermined based on the original address and compression parameters.
2Adaptability or versatility
If sequential writing to contiguous addresses is used, then simple buffer management is achieved, but non-sequential compression and transposed data storage are not accommodated
Solution Approach 1:
The patent changes the addressing parameter from sequential to non-sequential by introducing a mathematical relationship between the original address, compression ratio, and destination address. The equations transform the simple sequential address increment into a calculated address that reflects the compression ratio and enables non-sequential storage patterns.
Solution Approach 2:
The patent introduces dynamic address calculation that adapts to different compression ratios and data patterns. Rather than fixed sequential addressing, the destination address dynamically adjusts based on the compression ratio and original address, enabling flexible storage configurations including transposed data storage.
3Productivity
If a history buffer is used to accumulate data samples, then compression can proceed, but immediate writing without delay is not possible
Solution Approach 1:
The patent skips the buffer accumulation step entirely by directly calculating the destination address for each compressed data element. This allows the compression process to rush through to immediate writing without the time-consuming buffer accumulation phase, as the address calculation enables direct write-to-memory operation.
Data Source
AI summary
Disclosed embodiments include a system having a first memory for storing a plurality of data quantities, each data quantity consisting of a first number of bits, and a second memory for storing a plurality of compressed data quantities, each compressed data quantity consisting of a second number of bits that is less than the first number of bits. The system includes circuitry for reading data quantities from the first memory and for writing compressed data quantities, corresponding to respective read data quantities, to non-sequential addresses in the second memory. The circuitry for reading data quantities from the first memory is for reading along a read orientation selected from one of row-orientation or column-orientation from the first memory, and the circuitry for writing compressed data quantities in the second memory is for writing along a write orientation in the second memory that differs from the read orientation.