Memory Compression via Non-Volatile Memory Expanders
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Solution Overview
Problem
Current processor memory architectures with directly attached memory face limitations in bandwidth and memory capacity, particularly for applications requiring large memory and bandwidth, such as server consolidation and virtualization, due to insufficient memory bandwidth to support memory compression and associativity.
Innovation Solution
The implementation of memory expander nodes with non-volatile memory and memory expander logic that provide additional bandwidth and capacity by storing compressed data and implementing memory compression and multi-way associativity, allowing for dynamic allocation of memory channels between compressed and uncompressed data regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory compression is implemented in conventional attached memory, then memory capacity is expanded, but memory bandwidth is insufficient to support compression operations
Solution Approach 1:
The memory system is segmented into directly attached memory for high-speed access and remote memory expanders for additional capacity. This segmentation allows compression operations to occur in the remote memory without consuming the limited bandwidth of directly attached memory, resolving the contradiction between expanding memory capacity and preserving bandwidth for compression operations.
Solution Approach 2:
Memory expander logic acts as an intermediary between the processor and remote memory, handling compression operations locally at the expander. This intermediary approach allows compression to occur without burdening the processor or consuming the limited bandwidth of directly attached memory, enabling capacity expansion while maintaining bandwidth availability.
2Adaptability or versatility
If more memory is added to increase memory-to-processor core ratio, then virtualization capability is improved, but bandwidth limitations are exceeded
Solution Approach 1:
The system transitions from a single-dimension memory architecture (directly attached memory) to a multi-dimensional architecture by adding remote memory expanders connected through memory channels. This dimensional expansion allows the system to provide large memory capacity for virtualization while maintaining adequate bandwidth through the distributed architecture, as not all memory operations require processor-accessible bandwidth simultaneously.
3Quantity of substance
If compression logic is added to implement memory compression, then memory capacity is increased, but device complexity increases
Solution Approach 1:
Compression logic is extracted from the processor and placed in the memory expander nodes. This extraction allows the processor to remain simple while still enabling compression functionality through the distributed logic in the memory expanders, resolving the contradiction between increasing memory capacity through compression and maintaining device simplicity.
Data Source
AI summary
A method, an apparatus and a program product may enable scalable bandwidth and memory for a system having processor with directly attached memory. Multiple memory expander microchips may include non-volatile memory to provide additional memory bandwidth and capacity while in communication with the processor. The uncompressed data region may be implemented with standard high speed dynamic random access memory. The less frequently accessed compressed data region may be implemented with non-volatile memory to leverage its benefits of higher density, more capacity, and lower power compared to DRAM. Memory and bandwidth allocation between may be dynamically adjusted.