Memory Compression in Multi-Node Server Systems

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Solution Overview

Problem

Current computer memory architectures with directly attached processors face limitations in bandwidth and memory capacity, particularly in supporting memory compression and associativity, which are essential for high-performance applications like server consolidation and virtualization, due to insufficient memory bandwidth.

Innovation Solution

The introduction of memory expander nodes with memory expander logic and channels that implement memory compression and multi-way associativity, providing additional bandwidth and capacity while managing both compressed and uncompressed data, and dynamically adjusting memory allocation to optimize performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If memory is attached directly to the processor, then memory access speed is improved, but total available bandwidth and memory capacity are limited

Engineering Contradiction:
Improvememory access speedVSAvoidmemory capacity
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The memory system is divided into directly-attached memory (for high-speed access) and remote memory (for expanded capacity). The memory controller segments memory management into local and remote portions, allowing the system to achieve both fast access speeds for frequently used data and large total capacity through the combined memory resources.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If memory compression is implemented, then memory capacity is expanded, but memory bandwidth consumption increases

Engineering Contradiction:
Improvememory capacityVSAvoidmemory bandwidth
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

A memory expander device is introduced as an intermediary between the processor and remote memory. This device includes compression logic that performs memory compression and decompression operations, managing bandwidth consumption by compressing data before transfer to remote memory and decompressing when needed, thereby expanding capacity while controlling bandwidth usage.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If virtualization is implemented, then processor utilization is improved, but memory to processor-core ratio must increase

Engineering Contradiction:
Improveprocessor utilizationVSAvoidmemory capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The memory system provides universal access to both directly-attached and remote memory resources for multiple virtual machines. The memory controller manages memory allocation dynamically, allowing virtualized environments to access a pooled memory resource that combines local and remote memory, thereby supporting high processor utilization across multiple VMs without requiring proportional memory for each core.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Quantity of substance

If compression logic is added to enable memory compression, then memory capacity is expanded, but device complexity increases

Engineering Contradiction:
Improvememory capacityVSAvoidsystem complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The memory expander device serves as an intermediary that consolidates compression logic, cache memory, and remote memory interface in a single component. This approach expands memory capacity through compression while managing device complexity by centralizing the compression functionality in a dedicated memory expander rather than distributing it across multiple components.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7966455B2Memory compression implementation in a multi-node server system with directly attached processor memory
Publication Date: 2011.06.21 LENOVO INT LTD
  • US7966455B2 patent drawing
  • US7966455B2 patent drawing
  • US7966455B2 patent drawing

AI summary

A method, apparatus and program product enable scalable bandwidth and memory for a system having processor with directly attached memory. Multiple memory expander microchips provide the additional bandwidth and memory while in communication with the processor. Lower latency data may be stored in a memory expander microchip node in the most direct communication with the processor. Memory and bandwidth allocation between may be dynamically adjusted.