Semiconductor Memory Compression Test Mode Circuit
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in efficiently testing memory banks due to high peak current requirements and interference noise during data compression tests, making it difficult to determine the status of specific memory banks and perform repairs.
Innovation Solution
A semiconductor memory device with a compression test mode that includes a memory unit, timing circuit, compression circuit, and signal distribution circuit, where memory banks are divided into activating groups, and control signals are generated to sequentially activate sensing amplifiers, allowing data to be compressed and signals distributed among test pads in rotation, reducing peak current and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all banks are simultaneously activated during compression test, then test speed is improved, but peak current increases and interference noise is introduced
Solution Approach 1:
The memory banks are divided into multiple activating groups, and the compression test is performed by sequentially activating each group rather than all banks simultaneously. This segmentation reduces the peak current required at any given time while maintaining comprehensive test coverage across all banks.
2Productivity
If all banks are simultaneously activated during compression test, then test speed is improved, but interference noise increases
Solution Approach 1:
By dividing banks into activating groups and testing them sequentially, the simultaneous switching activity that causes interference noise is eliminated. Each group is tested in isolation, reducing noise while maintaining test efficiency.
3Productivity
If compress-data of all banks is output at one time, then test efficiency is improved, but ability to identify specific defective banks is lost
Solution Approach 1:
The compress-data output is segmented by activating group, with each group's data output separately. This allows the tester to identify which specific group contains defective banks while maintaining the efficiency of compression testing.
Solution Approach 2:
A signal distribution circuit is introduced as an intermediary between the compression circuit and the tester. This circuit distributes the compress-data to multiple test pads in rotation, enabling both efficient compression testing and identification of specific defective banks through the rotation pattern.
4Measurement precision
If compress-data is distributed among multiple test pads in rotation, then bank identification capability is improved, but device complexity increases
Solution Approach 1:
The signal distribution circuit acts as an intermediary that enables precise bank identification by distributing compress-data to multiple test pads in a controlled rotation pattern. While this adds some complexity, it provides the necessary capability to identify specific defective banks that would otherwise be lost in aggregated compression data.
Data Source
AI summary
A semiconductor memory device having a compression test mode is provided. The semiconductor memory device comprises a memory unit, i test pads, a timing circuit, a compression circuit, and a signal distribution circuit. The memory unit comprises m memory banks divided into n activating groups, wherein each bank comprises a plurality of sensing amplifiers for sensing and amplifying data in bit lines. The timing circuit sequentially generates n control signals each for activating a plurality of sensing amplifiers in one of the n activating groups. The compression circuit compresses data sensed and amplified by the plurality of sensing amplifiers in each bank in a compression test mode. The signal distribution circuit distributes signals output from the compression circuit among the i data pads in rotation. The integer n and the integer i are adjustable.