Memory-Computing Chip Layout for Lower-Power Data Paths
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Solution Overview
Problem
The von Neumann architecture's memory and processor separation limits computing capability due to mismatched transmission speeds, reducing overall system performance and increasing power consumption.
Innovation Solution
A memory-computing integrated chip architecture with arrays of memory-computing integrated cells coupled to peripheral circuit IP cores via communication paths arranged based on operation properties and arrangements, allowing flexible configuration and maximizing computing power while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is frequently transmitted between the processor and the memory in von Neumann architecture, then the computing capability of the processor can be maintained, but the power consumption increases and the overall system performance is reduced due to speed mismatch
Solution Approach 1:
The patent merges the memory and computing functions into a single integrated chip architecture. The memory-computing integrated cells combine storage elements (e.g., DRAM cells) with computing elements (e.g., transistors for logic operations) on the same chip, eliminating the need for frequent data transmission between separate memory and processor components. This integration directly reduces power consumption while maintaining computing capability.
2Device complexity
If the transmission speed of the memory cannot match the operating speed of the processor, then the processor structure can be simplified, but the operating speed of the processor is significantly reduced
Solution Approach 1:
By integrating memory and computing functions into the same chip, the patent eliminates the speed mismatch problem between separate memory and processor components. The memory-computing integrated cells enable direct interaction between storage and computation operations, allowing the processor to operate at full speed without waiting for memory transmission.
Solution Approach 2:
The patent segments the computing function into multiple memory-computing integrated cells that can be distributed across the chip. This segmentation allows parallel processing operations to occur simultaneously with memory operations, effectively increasing the operating speed while maintaining a relatively simple overall structure.
3Ease of manufacture
If communication paths are arranged without considering operation properties and array arrangements, then the configuration process is simplified, but the computing power utilization is reduced and power consumption increases
Solution Approach 1:
The patent implements a dynamic communication path arrangement system that adapts to different operation properties and array configurations. The communication paths can be dynamically configured based on the specific computing task requirements, allowing optimal utilization of computing power while maintaining ease of manufacture through standardized path designs that can be programmatically controlled.
Data Source
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AI summary
The present disclosure relates to the technical field of memory-computing integrated chips, and in particular, to a memory-computing integrated chip architecture, a packaging method and an apparatus for a memory-computing integrated chip. The memory-computing integrated chip architecture includes: a plurality of first chips, each integrated with one or more arrays of memory-computing integrated cells, wherein the one or more arrays of memory-computing integrated cells are used for computing with received data; and one or more second chips, each integrated with one or more peripheral circuit IP cores, wherein the one or more arrays of memory-computing integrated cells are coupled to the one or more peripheral circuit IP cores via one or more communication paths, and wherein the one or more communication paths are arranged based on one or more of an operation property and an arrangement of the one or more arrays of memory-computing integrated cells of the plurality of first chips.