Memory-Computing Chip Layout for Faster Data Paths
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Solution Overview
Problem
The von Neumann architecture's limitations in data transmission speed between processor and memory reduce computing capability, leading to performance issues in computing systems.
Innovation Solution
A memory-computing integrated chip architecture with arrays of memory-computing integrated cells coupled to peripheral circuit IP cores via communication paths arranged based on operation properties and arrangements, allowing flexible configuration and maximizing computing power while reducing power consumption and disorderly communication paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is frequently transmitted between processor and memory in von Neumann architecture, then computing capability is improved, but transmission speed limitation reduces overall system performance
Solution Approach 1:
The patent merges memory and computing units into an integrated memory computing chip, where memory cells directly perform computing operations on stored data. This eliminates the need for frequent data transmission between separate processor and memory components, resolving the speed bottleneck while maintaining computing capability.
Solution Approach 2:
The patent transitions from the traditional von Neumann architecture's sequential data flow to a three-dimensional stacked architecture with multiple computing layers and memory layers connected via through-silicon vias. This spatial reorganization enables parallel data access and computation across multiple layers, dramatically increasing effective data transmission speed.
2Device complexity
If communication paths are arranged without considering operation properties, then device complexity is reduced, but computing power utilization is suboptimal and power consumption increases
Solution Approach 1:
The patent applies local quality by arranging communication paths based on specific operation properties and data access patterns of different memory computing arrays. High-frequency communication paths are optimized for speed, while low-frequency paths are optimized for power efficiency, allowing each communication path to be tailored to its specific functional requirements rather than using a uniform approach.
Data Source
AI summary
The present disclosure relates to the technical field of memory-computing integrated chips, and in particular, to a memory-computing integrated chip architecture, a packaging method and an apparatus for a memory-computing integrated chip. The memory-computing integrated chip architecture includes: a plurality of first chips, each integrated with one or more arrays of memory-computing integrated cells, wherein the one or more arrays of memory-computing integrated cells are used for computing with received data; and one or more second chips, each integrated with one or more peripheral circuit IP cores, wherein the one or more arrays of memory-computing integrated cells are coupled to the one or more peripheral circuit IP cores via one or more 10 communication paths, and wherein the one or more communication paths are arranged based on one or more of an operation property and an arrangement of the one or more arrays of memory-computing integrated cells of the plurality of first chips.