In-Memory Computing Element With Resistive Summation and Subtraction
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Solution Overview
Problem
Traditional computing systems face performance and energy bottlenecks due to data movement between processors and memory, particularly in applications like neural network processing, where in-memory computing can improve performance but is not efficiently addressed by existing technologies.
Innovation Solution
The development of a basic computing element that includes a resistive network with a pair of resistors and a memory switch, allowing for current or voltage division and routing to summation or subtraction buses, enabling arithmetic operations like multiplication, addition, and subtraction in an analog domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is stored in separate memory and processed by a separate processor, then the system structure is simple and easy to manufacture, but data movement between processor and memory creates performance and energy bottlenecks
Solution Approach 1:
The patent merges memory storage and computational processing into a single integrated structure. Memory cells are directly coupled with computing elements (resistive networks with switches) within the same memory array, eliminating the need for separate processors. This allows data to be processed in-place without movement between separate components, resolving the bottleneck while maintaining memory-like simplicity.
Solution Approach 2:
The memory cells serve dual functions: storing data and performing computational operations. The same memory infrastructure that holds data also executes arithmetic and logic functions through the integrated computing elements, making the system universally capable of both storage and processing without requiring separate specialized components.
2Productivity
If in-memory computing is implemented, then processing performance improves, but existing technologies do not efficiently address the computational tasks
Solution Approach 1:
The computing function is segmented into basic computing elements that can be systematically integrated into existing memory arrays. Each computing element is a discrete unit (resistive network with switch) that can be manufactured using standard memory fabrication processes, enabling scalable implementation without requiring entirely new manufacturing approaches.
Solution Approach 2:
The memory system performs its own computational operations using its inherent structure and materials. The resistive networks and switches within the memory cells directly execute arithmetic and logic functions on the stored data, eliminating the need for external processing infrastructure and simplifying implementation.
3Quantity of substance
If high-density memory structures are used, then storage capacity increases, but computational integration becomes more difficult
Solution Approach 1:
The computing elements are merged directly into the memory cell structure at the same density level. The resistive networks and switches are integrated within the same fabrication layers and spatial footprint as the memory cells, allowing high-density storage and computation to coexist without increasing overall system complexity or requiring additional integration layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides improved memory speed, endurance, reliability, and low power consumption, achieving 10-100 times higher density and lower cost than current implementations, while enabling high-performance parallel computation architectures.
Implementation Method 1
Each basic computing element includes a first resistor having a first resistance value and a second resistor having a second resistance value. The first resistor couples an input voltage to an output voltage to be provided to a next basic computing element of the plurality of basic computing elements.
Implementation Method 2
The first resistor and second resistor are configured as a current or voltage divider.
Implementation Method 3
The second resistor of the resistive network is coupled to an input of a memory switch that routes current received through the second resistor to either a summation bus or a subtraction bus.
Data Source
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AI summary
A computing device and basic computing element is disclosed. The example computing device includes a resistive network comprising a plurality of basic computing elements coupled in series. The basic computing elements include a first resistor having a first resistance value and a second resistor having a second resistance value. The first resistor couples an input voltage to an output voltage to be provided to a next basic computing element of the plurality of basic computing elements. The second resistor of the resistive network is coupled to an input of a memory switch that routes current received through the second resistor to either a summation bus or a subtraction bus. The computing device also includes a signal processing unit coupled to the summation bus and the subtraction bus.