Memory Device Concurrent Repair Detection Circuit

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Solution Overview

Problem

Current memory devices face challenges in detecting and addressing concurrent repair cases where both low and high banks of the same column, unsupported by a circuit, are simultaneously repaired, leading to reduced yield and operational failures.

Innovation Solution

A memory device system that includes a column repair controller and a method for detecting concurrent repair by storing and comparing test information from both low and high bank column lines, using CAM data to identify and manage repair operations, thereby preventing access failures and increasing yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If concurrent repair cases are not detected, then manufacturing yield is reduced, but implementing detection increases device complexity

Engineering Contradiction:
Improvemanufacturing yieldVSAvoiddetection circuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent creates a copy of the repair column information from the system block into a separate detection circuit. This copy allows the detection of concurrent repair cases without modifying the original repair mechanism, thereby increasing yield through detection while maintaining the existing repair functionality and minimizing added complexity.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent introduces an intermediary detection circuit that mediates between the repair column information storage and the control logic. This intermediary component processes the repair information to detect concurrent repair cases, separating the detection function from the repair execution and allowing yield improvement without directly complicating the core repair mechanism.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If concurrent repair cases are detected and prevented, then access failure rate decreases, but detection and processing time increases

Engineering Contradiction:
Improveaccess failure rateVSAvoiddetection and processing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary detection of concurrent repair cases by comparing repair column information before access operations occur. By detecting and preventing concurrent repair cases in advance, the system avoids access failures during normal operation, improving reliability while minimizing the time penalty to only the detection phase rather than affecting operational performance.

Inventive Principle:
Principle #10Preliminary action

3Ease of repair

If repair column information is stored in the system block, then repair functionality is maintained, but detection of concurrent repair cases becomes difficult

Engineering Contradiction:
Improverepair functionalityVSAvoidconcurrent repair detection
Core Design Contradiction:
Ease of repairVSDifficulty of detecting and measuring

Solution Approach 1:

The patent segments the repair information handling into two parts: the system block stores the original repair column information to maintain repair functionality, while a separate detection circuit creates and processes a copy of this information for detection purposes. This segmentation allows both repair functionality and concurrent repair detection to coexist without interfering with each other.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11581057B2Memory device and method of operating the same
Publication Date: 2023.02.14 MIMIRIP LLC
  • US11581057B2 patent drawing
  • US11581057B2 patent drawing
  • US11581057B2 patent drawing

AI summary

A memory device includes a system block for storing test information and includes a data block including memory cells connected to a plurality of low bank column lines and a plurality of high bank column lines. The memory device also includes a column repair controller configured to detect, based on the test information, a concurrent repair column line in which a low bank column line among the plurality of low bank column lines and a high bank column line the plurality of high bank column lines corresponding to the same column address are concurrent repaired.