Semiconductor Memory Device Conductive Pattern Width Variation
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration density due to the need for expensive equipment to form finer patterns, leading to a demand for three-dimensional semiconductor memory devices with improved electrical characteristics and reliability.
Innovation Solution
A semiconductor memory device design featuring a stack structure with bit lines, semiconductor patterns, and conductive patterns, where the width of the conductive patterns increases as distance from the semiconductor patterns, along with a dielectric layer between them, and a method involving etching processes to form recess regions and conductive patterns, enhancing integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices use finer patterns to improve integration density, then integration density increases, but manufacturing cost increases due to expensive equipment requirements
Solution Approach 1:
The patent transitions from two-dimensional planar structures to three-dimensional vertically stacked structures. Memory cells are arranged in multiple layers with bit lines, word lines, and conductive patterns extending in different spatial directions, enabling higher integration density without requiring proportionally finer pattern dimensions that would demand expensive manufacturing equipment
2Reliability
If the width of conductive patterns is increased to improve electrical connections, then reliability improves, but area occupied increases
Solution Approach 1:
Conductive patterns are configured to extend in multiple directions including vertical stacking, allowing increased effective conduction area and improved electrical reliability without proportionally increasing the planar footprint. The three-dimensional arrangement enables broader electrical connections through vertical extension rather than horizontal expansion
Solution Approach 2:
Conductive patterns are inserted within or overlapping other conductive patterns in the vertical dimension. Second conductive patterns include insertion portions that extend into first conductive patterns, creating nested configurations that enhance electrical connectivity while efficiently utilizing vertical space rather than consuming additional planar area
Data Source
AI summary
A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.