Nonvolatile Memory Configuration Processing Clock Control
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Solution Overview
Problem
The existing nonvolatile memory apparatuses require a lengthy time to process configuration information during power initialization due to the substantial number of configuration data groups, which necessitates a technology to shorten this processing time while ensuring operational stability.
Innovation Solution
A nonvolatile memory apparatus that includes a configuration information processing circuit capable of determining majorities of configuration data groups using a first control clock signal during the initial power-up stage and a second control clock signal with a shorter cycle once power is stabilized, allowing for sequential processing and output of determination results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of configuration data groups is increased to improve reliability and coverage, then the reliability is improved, but the configuration information processing time is extended
Solution Approach 1:
The patent applies preliminary action by pre-organizing configuration data into multiple groups that can be processed in parallel. The configuration information storage block is divided into multiple sub-blocks, each handling specific configuration data groups. This pre-structure enables simultaneous processing of multiple configuration parameters, reducing the overall processing time while maintaining comprehensive coverage and reliability.
Solution Approach 2:
The patent segments the configuration information processing into multiple parallel pathways. The configuration data is divided into multiple groups stored in separate sub-blocks, each with dedicated decoding circuits. This segmentation allows concurrent processing of different configuration parameters, transforming a sequential bottleneck into parallel operations that reduce total processing time while maintaining data integrity.
2Device complexity
If a single clock signal is used for configuration data processing, then the circuit design is simple, but the processing speed is limited
Solution Approach 1:
The patent implements dynamic clock signal distribution where a single external clock source is dynamically divided into multiple clock signals with different frequencies using clock dividing circuits. Each configuration sub-block receives an appropriately divided clock signal based on its processing requirements. This dynamic approach allows faster processing speeds for critical configuration data while maintaining simple external interface design.
Solution Approach 2:
The patent adds a frequency dimension to the clock signal system. Instead of using multiple external clock sources (spatial dimension), it divides a single clock signal into multiple frequency components through clock dividing circuits. This frequency dimensionality allows different configuration sub-blocks to operate at different speeds simultaneously, increasing overall processing throughput without increasing external circuit complexity.
Data Source
AI summary
A nonvolatile memory apparatus includes a memory device including a configuration information storage block for storing configuration data groups. A configuration information processing circuit is configured to determine majorities of configuration data groups, which are outputted from the memory device during a first period as an initial stage of a power-up operation, under the control of a first control clock signal. The configuration information processing circuit is also configured to determine majorities of configuration data groups, which are outputted from the memory device during a second period after the first period, under the control of a second control clock signal having a cycle shorter than the first control clock signal.